Altera has taken a three-pronged approach to help customers tackle power consumption in their systems:
- Silicon Level: Stratix® II 90-nm Silicon Power Optimization: For a competitive comparison, visit the Stratix II and Virtex-4 Power Comparison page
- Logic Design Level: PowerPlay Power Analysis and Optimization Technology
- System Level: Power Management Resource Center
In addition, if you wish to learn how Stratix II FPGAs compare with other FPGAs in the industry, please visit the Stratix II and Virtex-4 Power Comparison page.
This page focuses on the silicon level: Stratix II 90-nm silicon power optimization. It provides an overview of semiconductor power consumption and techniques for lowering power consumption in silicon (see Table 1 below). Figure 1 depicts the components of total power for a high-performance FPGA design.
Figure 1. Typical Power Consumption for a High-Performance FPGA Design
Note to Figure 1:
1. Component of Dynamic Power Consumption
Semiconductor manufacturers use many techniques to lower power consumption at the silicon level. For example, using a low-k dielectric technique affects dynamic power consumption (internal and I/O transistor power consumption) by approximately 10 percent. Figure 1 shows that internal and I/O transistor power consumption is a major component of total power consumption. Therefore, a 10 percent power reduction of these components is significant. Other techniques can impact dynamic and static power consumption, such as adjusting the transistor threshold voltage. This adjustment involves deciding what the power-performance tradeoff will be and setting the threshold voltage accordingly for each functional group of transistors. Finally, some techniques will impact static power consumption such as the use of triple oxide (specifically impacts configuration RAM only).
Some of the techniques Altera used to optimize Stratix II FPGA performance while keeping power consumption as low as possible are described below.
Background
The semiconductor industry continually moves to provide faster and cheaper devices for their customers. One way this is achieved is through finer process geometries (such as moving from 130 nm to 90 nm) which reduces die size for an equivalent capacity device. Finer process geometries enable smaller transistors, resulting in more transistors in a fixed amount of space. Due to the shorter distance between transistors and use of lower voltages, performance is increased when moving to a finer process geometry.
There are two main components of power consumption in CMOS devices. Dynamic power consumption is power that is dissipated through the switching of I/O transistors and internal transistors. Static power consumption is the power that is dissipated while a transistor is not switching. Internal static power disappation is caused by leakage current across the transistor, while I/O static power dissapation is mostly caused by the use of resistively terminated I/O standards, which draw a static current. Static and dynamic power consumption combine to form the total power consumption of the device.
The use of finer semiconductor process geometries (specifically the 90-nm geometry) has caused static power consumption to increase. As the size of the transistor shrinks and lower voltages are used, a greater sub-threshold leakage current occurs in the transistor channel when the transistor is in the off state. Consequently, static power consumption rises significantly with the use of the 90-nm process.
Dynamic power is affected in two ways by process scaling. First, the use of smaller feature sizes and lower voltages significantly reduces dynamic power consumption. However, higher device operating frequencies are possible in 90-nm technology, and, since dynamic power increases with operating frequency, designs that make full use of the speed of 90-nm technology will see less reduction in dynamic power.
Techniques for Lowering Power Consumption in Silicon
As a result of the expected blanket increase in power consumption for smaller process geometries, semiconductor manufacturers use various techniques to optimize power consumption, both in the dynamic and static domains. There are many techniques that can be employed when reducing power in silicon. Table 1 describes some examples.
| Table 1. Silicon Design & Process Techniques for Reducing Power Consumption at 90 nm | |||
| Technique | Power Benefit | Specific Effects | Used in Stratix II |
|---|---|---|---|
| Increase Vt (Threshold Voltage) | Static Power Reduced |
|
Yes |
| Increase Transistor Length |
Static Power Reduced |
|
Yes |
| Triple Oxide | Static Power Reduced |
|
No |
| Architectural Changes: 4-Input LUT to 7-Input Variable Adaptive Logic Module (ALM) |
Active Power Reduced |
|
Yes |
| Process Changes: FSG to Low-K Dielectric |
Active Power Reduced |
|
Yes |
| Lower I/O Pin Capacitance | Active Power Reduced (I/O) |
|
Yes |
| Power Effiecient Clocking Structure | Active Power Reduced |
|
Yes |
Manufacturers must intelligently employ the techniques described in Table 1 to optimize performance while minimizing power consumption in silicon. Altera took these steps to help keep silicon power consumption as low as possible without compromising customer performance requirements or manufacturability. Altera® FPGAs generate less heat and consume less system power. You will benefit from using Altera FPGAs because lower silicon heat lowers the need for using heat-dissipating technology, improves system reliability, and simplifies the design process.
