Stratix II and Virtex-4 Power Comparison

Having an accurate FPGA power estimate is important to avoid surprises late in the design and prototyping phase. Inaccurate estimates can be costly and cause design issues, including board respins, changes to power circuitry, changes to cooling solutions, and degraded reliability.

The benchmarked data that follows describes how, unlike Virtex-4 and the Xilinx ISE XPower tool, Stratix^® II FPGAs and the Quartus^® II PowerPlay power analysis tool allow you to meet your total device power budget without surprises:

• The Altera^® Quartus II PowerPlay power analyzer tool is very accurate (to within 20 percent), while Xilinx’s tools are significantly less accurate.
• Stratix II devices exhibit lower dynamic power compared to Virtex-4, resulting in total device power that is equal.

Altera’s Board of Truth (see Figure 1) was designed and constructed for fair, head-to-head power measurements of Stratix II EP2S60 devices and Virtex-4 LX60. This board features electrically isolated, identical layouts for both devices and allows independent measurement of each device power rail. The board was used in the generation of hardware power consumption data in the analysis that follows. For more technical details on this data and how it was measured, download the white paper Stratix II vs. Virtex-4 Power Comparison with Power Estimation Accuracy (PDF).

Figure 1. The Board of Truth, with an EP2S60 and LX60 Device Used To Compare Power

By far, the best estimate of dynamic power is obtained by measuring a design in-system. This is done by measuring the amount of current the FPGA is drawing on each power rail at the operating frequency. Please note that static power results from single-unit measurements are not meaningful due to significant unit-to-unit static power variation. The vendor-provided worst-case specification should be used instead (as explained in the Static Power section below).

Quartus II PowerPlay Accuracy vs. Competition

Accurate FPGA power estimation is essential to correct thermal solution and power supply design, and also enables you and the FPGA software to optimize the design for power. Altera’s PowerPlay tools—the Early Power Estimator spreadsheet and the Quartus II PowerPlay power analyzer—provide accurate estimation capabilities, with Quartus II software version 5.0 service pack 1 (SP1) estimating power to within 20 percent.

Figure 2 compares bench-measured power with the estimates produced by the Quartus II software version 5.0 SP1 PowerPlay power analyzer and ISE 7.1i SP2 XPower. A variety of designs were selected to provide coverage of many of FPGA functions. While Quartus II PowerPlay results are within 20 percent of silicon, the ISE XPower results show a significant spread, underestimating by up to 8x and over-estimating by up to 3x.

Figure 2. Estimation Error of Dynamic Power for 20 Individual Designs From Quartus II PowerPlay and ISE XPower

Notes:
* The Xilinx ISE XPower tool crashes when reading large complex Value Change Dump (.vcd) files. No XPower estimates are available for these designs.
** For a more detailed version of this graph and other technical details, view the white paper Stratix II vs. Virtex-4 Power Comparison with Power Estimation Accuracy (PDF).

Lower Dynamic Power

To compare the dynamic power of Stratix II FPGAs to Virtex-4 FPGAs, Altera measured results across a variety of designs selected to provide coverage of many of FPGA functions (see Figure 3). Stratix II FPGAs exhibit a substantial power advantage on nearly all RAM configurations, and consume equivalent or better dynamic power in block-level logic and digital signal processing (DSP) designs. Even in a 1,024 x 18 RAM application that optimally maps to Virtex-4 BRAM, Stratix II FPGAs are only at a 21 percent disadvantage—compared to the 5x factor claimed by the competition. On complete user designs—including an MD5 cryptographic hash function, an FM Radio transceiver, a 3DES cipher core, a Rijndael core, and a JPEG encoding core—Stratix II FPGAs exhibit up to 54 percent lower dynamic power. The Beamforming design is a full HDL customer RADAR imaging application that employs DSP blocks, RAM blocks, and logic. The Beamforming results show that Stratix II FPGAs have a 47 percent advantage.

Figure 3. Stratix II Dynamic Power Relative to Virtex-4, Based on Hardware Measurements

Note:
* For a more detailed version of this graph and other technical details, view the white paper Stratix II vs. Virtex-4 Power Comparison with Power Estimation Accuracy (PDF).

The measured Stratix II FPGA dynamic power advantage can be explained through several silicon design innovations not present in Virtex-4. Stratix II FPGAs have 20 percent lower metal capacitance because of the use a low-k intermetal dielectric (k = 2.9) compared to Virtex-4’s “reduced-k” (k = 3.6). The innovative adaptive logic module (ALM) further reduces logic requirements, offering up to half the power for logic-intensive applications. Additionally, the TriMatrix memory architecture gives you the right size memory for your application, resulting in up to one-third the RAM power vs. Virtex-4.

For more technical details on this data and how it was measured, download the white paper Stratix II vs. Virtex-4 Power Comparison with Power Estimation Accuracy (PDF).

Static Power

Static power arises from currents in the FPGA that are independent of operation frequency (such as leakage current across a transistor). Because static power can vary from one device to another (for all CMOS devices), measured static power is only relevant to determine if that particular device meets the manufacturer's device specification. The only way to meaningfully compare static power between devices is to compare worst-case specifications, summed across all power supply rails.

Table 1 gives a specification-based comparison of Stratix II and Virtex-4 static power at 85°C junction temperature on worst-case silicon. Note that the Stratix II worst-case specification used is for Stratix II industrial silicon, which has a lower static power specification than Stratix II commercial-grade devices. Values are derived from the Early Power Estimator 3.0 for Stratix II FPGAs, and Web Power Tool 7.1 for Virtex-4 FPGAs. Devices have been lined up by equivalent logic capacity. Although, note that EP2S15 and EP2S60 devices are lined up with notably less dense Virtex-4 devices (conservative comparison). For more information on logic density comparisons, read the Stratix II vs. Virtex-4 Density Comparison (PDF) white paper.

Note that Xilinx VCCAUX supply can account for up to 25 percent of its static power and is thus important to consider. Overall, Virtex-4 has a small static power advantage. However, this difference is outweighed by the Stratix II dynamic and I/O power advantage. To offset this difference even further, each Virtex-4 DCM adds 28 mW of static power when it is used in the design, compared to the Stratix II FPGA's phase-locked loop (PLL) static power, which is 3 mW.

For more technical details on static power, download the white paper Stratix II vs. Virtex-4 Power Comparison with Power Estimation Accuracy (PDF).

Up to 50 Percent Lower I/O Power

Altera employed advanced circuit design techniques to reduce the total capacitance on each Stratix II I/O pin. This results in faster I/O pins, improved signal integrity, and a reduction in I/O power. The lower pin capacitance reduces FPGA power on output pins, and reduces the power of driving devices on input pins, lowering overall system power. Table 2 shows the measured pin capacitance for Stratix II and Virtex-4 FPGAs.

For more technical details on I/O power and measured I/O power data, download the white paper Stratix II vs. Virtex-4 Power Comparison with Power Estimation Accuracy (PDF).

Total Power

When analyzing total power for a complete user design for Virtex-4 and Stratix II FPGAs, all three components of power should be considered: static power, dynamic power, and I/O power. While it is important to measure total power for your specific design, experiments using our design database indicate that total power consumption in the typical design will be equal or better in Stratix II FPGAs. Benchmarks from 99 customer designs show that dynamic power is responsible for 67 percent of total device power on average. Comparatively, static power and I/O power are responsible for 21.7 percent and 11.2 percent, respectively, for total device power. The dominant component of total device power is dynamic power and, therefore, the dynamic power advantage that Stratix II FPGAs have will easily negate any Virtex-4 static power advantage.

18 Percent Higher Performance

Performance leadership was a major goal when designing Stratix II FPGAs. Benchmarks show that an average of 18 percent higher performance is achieved over Virtex-4, as shown in Figure 4. The goal of lowering total device power was also achieved by providing lower dynamic power and comparable static power, without sacrificing performance.

The Stratix II vs. Virtex-4 Performance Comparison (PDF) white paper contains detailed discussion about the above benchmark data and results analysis.

Figure 4. The Altera Zone (Note 1)

Note:

1. This benchmark data uses the fastest speed grade for FPGA families under test (Altera Stratix II and Cyclone^®  II families, and Xilinx’s Virtex-4 and Spartan-3 families), and is based on results from Quartus II software version 5.0 and ISE 7.1i service pack 1.

Paths to Lower Power: Cyclone II and HardCopy II Devices

For designs with lower performance requirements and/or feature requirements, Cyclone II FPGAs offer 35 percent lower dynamic power and one-quarter the static power of Stratix II FPGAs. Additionally, the HardCopy^® II ASIC cost reduction path offers lower cost, higher performance, and 2.5x less total power. More information on Cyclone II and HardCopy II device power can be found on the following web pages.

• The Cyclone II Power Advantage
• HardCopy II ASICs