Differences between Stratix II & Stratix Devices

Stratix^® II FPGAs are based on the same industry-preferred feature set as the award-winning first-generation Stratix devices with the addition of many key enhancements. Stratix II devices offer several new features such as the new and innovative adaptive logic modules (ALMs), 1-Gbps source-synchronous signaling with dynamic phase alignment (DPA), and design security, among others.

Innovative Logic Structure

Stratix II devices have an innovative, highly-efficient logic structure that offers higher performance and higher density. With up to 180K equivalent LEs, Stratix II devices offer more than twice the capacity of first-generation Stratix devices.

The Stratix II device's ALMs delivers more logic capacity and faster performance in a smaller physical area. Because it permits inputs to be shared by adjacent look-up tables (LUTs), the new structure significantly reduces the total number of equivalent logic elements (LEs) required to implement any given function, and more importantly, reduces the number of logic levels in a given critical path. Multiple, independent functions can also be packed into a single ALM, further reducing logic resource requirements. This is important at the 90-nm node where interconnect delay assumes the larger proportion of the total FPGA delay and where reducing interconnect traversals is crucial to maximizing device performance. The ALM also offers the ternary adder function that reduces logic resource consumption for long adder trees.

In addition to increased resource usage efficiency, ALMs delivers an average of 50 percent faster core performance, and over twice the logic capacity, of prior-generation FPGAs. Support for internal clock frequency rates of up to 500 MHz and typical design performance at over 250 MHz means that designers can now get ASIC-like performance with the time-saving advantages of implementing their designs with programmable logic.

Design Security

To provide designers with a means to protect their systems, Stratix II devices support configuration bitstream encryption using the advanced encryption standard (AES) and a 128-bit non-volatile key. Each Stratix II device can be securely configured with an encrypted configuration file generated by Quartus^® II software and stored in an external configuration device. The Design Security web page has more information.

Source-Synchronous Signaling With Dynamic Phase Alignment

Stratix II devices give designers access to 152 receiver and 156 transmitter high-speed differential I/O channels capable of 1.040-Gbps performance. Each of these I/O channels includes dedicated serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for reliable data transfer, simplifying the complexity associated with implementing high-speed interface standards such as 10-Gbit Ethernet XSBI, SFI-4, SPI-4.2, HyperTransport™ technology, the RapidIO™ standard, and CSIX. The Stratix II Source-Synchronous Protocols page has more details.

Feature Comparison

The Stratix II architecture builds on the highly successful Stratix architecture and offers the same features as Stratix devices including the innovative TriMatrix^™ memory structure, speed-optimized digital signal processing (DSP) blocks, and advanced clock-management circuitry Table 1 summarizes the features offered by Stratix and Stratix II devices.

Note to Table 1:

1. PLLs = Phase-locked loops

Table 2 summarizes how Stratix devices compare with Stratix II devices in terms of available logic resources.

Related Links

• Stratix II Devices
• Stratix Devices
• Stratix II Device Family Features
• Stratix Device Family Features