No matter what next-generation system you are developing, the new 65-nm Stratix® III FPGA family combines lower power with higher performance and density to meet your most challenging design requirements.
Lowest Power
Stratix III FPGAs automatically maximize performance and minimize power consumption:
- Programmable Power Technology allows each logic array block (LAB), digital signal processing (DSP) block, and memory block to be set for either high speed or low power
- Selectable core voltage offers the option to use a core voltage of either 1.1 V or 0.9 V
- Quartus® II PowerPlay power analysis and optimization technology analyzes the power consumption requirements and automatically implements Programmable Power Technology
High Performance
Stratix III FPGAs provide a 25 percent improvement in performance over previous generations of Altera® FPGAs:
- Core operation up to 600 MHz and higher speed external memory interfaces and user I/O pins
- Quartus II TimeQuest timing analysis—the most advanced tool for design timing constraints compared to any programmable logic software
High Density
65-nm Stratix III FPGAs are the largest FPGAs in the industry with up to:
- 340K equivalent logic elements (LEs)
- 17 Mbits of memory
- 1,104 user I/O pins
Performance Enhancing Features
Altera’s new Stratix III FPGAs provide:
- Faster timing closure, to meet your next-generation design’s performance requirements
- A slower speed-grade device to achieve performance goals and reduce costs
- A mature process for risk-free design implementation and extra system-level margins
- The industry’s leading software tools to implement a design methodology for high-density, high-performance designs
Table 1 lists the next-generation differences between Stratix II and Stratix III FPGAs.
| Table 1. Next-Generation Stratix III Device Family Features | |||
| Feature | Stratix II Device Family | Stratix III Device Family | Next-Generation Design Value of Stratix III FPGAs |
|---|---|---|---|
| Process Technology | 90 nm | 65 nm | Highest performance and lowest power 65-nm FPGA |
| 1.2-V core voltage | 0.9- or 1.1-V core voltage | ||
| Power Consumption | Lowest dynamic power | Programmable Power Technology | 50 percent power reduction |
| Lowest dynamic and static power | |||
| Logic Density | Up to 180K LEs | Up to 340K LEs | Industry’s largest FPGA |
| Embedded Multipliers | Up to 384 18x18 multipliers capable of performing at up to 450 MHz | Up to 896 18x18 multipliers capable of performing at up to 550 MHz | Highest performance DSP capabilities in the industry |
| Ideal for video and image processing and wireless applications | |||
| I/O Banks | Dedicated I/O structures | Modular I/O banks with dedicated structures for LVDS and DDR | Maximum performance, flexibility, and efficiency |
| Up to 12 independent I/O banks per device | Up to 24 independent I/O banks per device | ||
| True-LVDS Maximum Data Rate | 311–1,040 Mbps | 125–1,250 Mbps | Higher bandwidth |
| Signal Integrity | Low pin capacitance | 8:1:1 user I/O to power/ground ratio | Best-in-class signal integrity |
| Programmable pre-emphasis | On-die and on-package decoupling | ||
| On-Chip Termination | Serial and differential on-chip termination | Serial, parallel, differential, and dynamic on-chip termination | Superior signal integrity |
| Reduce need for external termination | |||
| Design Security | 128-bit key length | 256-bit key length | Easiest to use with maximum security |
| Volatile | Volatile and non-volatile | ||
