Quartus® II software delivers the #1 performance and productivity for high-end 40-nm Stratix® IV FPGA designs, helping you to exceed your performance goals, meet your power budget requirements, and complete your design faster. Advanced place-and-route technology, physical synthesis, and the TimeQuest timing analyzer help you quickly close timing. Using the industry’s most comprehensive incremental compilation feature allows you to reduce your design cycle with shorter compile times. Plus, PowerPlay power analysis and optimization technology automatically minimizes your design’s power consumption.
The Leader in Productivity for High-End FPGA Designs
With all these productivity-enhancing features, Quartus II software can dramatically improve productivity compared to traditional high-density FPGA design flows:
- TimeQuest timing analyzer is an ASIC-strength timing analyzer with native support for the industry-standard SDC timing constraints format. The TimeQuest timing analyzer offers an easy-to-use GUI, SDC editor, and tool command language (Tcl) console to quickly and easily create timing constraints. In addition, the TimeQuest timing analyzer offers fast, interactive timing analysis and reporting to quickly reach timing closure.
- Incremental compilation is an industry first. This feature supports top-down and bottom-up, team-based design which delivers faster compilation times for design iterations while preserving performance.
- PowerPlay power analysis and optimization technology provides automated power optimization capabilities and helps you effectively manage power from design concept through implementation. It includes support for Stratix IV Programmable Power Technology.
- SOPC Builder is a system-level tool that eliminates mundane and error-prone system integration tasks and allows you to build systems in minutes.
- Nios® II processor provides a great degree of flexibility for a wide range of applications.
- Push-button physical synthesis technology and the automated Design Space Explorer simplify design optimization.
- Extensive cross-probing support between tools helps identify and correct design issues.
- The pin planner feature (PDF) enables easy I/O pin planning, assignment exploration, assignment, and validation.
- Complete command-line and Tcl scripting interfaces give you advanced scripting capabilities.
- Industry-leading compile times in Quartus II software are the lowest in the industry with compile times on average 3x faster than the nearest competing solutions.
- Multi-processor support in Quartus II software now supports parallel processing during compilation for computers with multiple processors. You can reduce compile times by an average of 15 percent.
- Memory requirements in Quartus II software typically are up to half the memory required by competing solutions, allowing you to avoid an "out of memory" error during compilation.
- Quartus II software is built in 32-bit and 64-bit versions for Windows operating systems. Quartus II 64-bit application software allows you to take advantage of computers with more than 4 Gbytes of memory when running Windows XP professional x64.
- Verification solutions include the following features:
- Capability to update memory and constants in-system without reconfiguring the device.
- Chip Planner shows hierarchical views of a design implemented in an Altera® device.
- SignalTap® II embedded logic analyzer and support for integration with external logic analyzers.
- Integration with all leading third-party EDA verification tools and methodologies.
The Leader in Performance for High-End FPGA Designs
Quartus II software enables the highest levels of performance and the fastest path to design completion for high-end Stratix IV FPGA designs. Quartus II design software and Stratix IV FPGAs offer a significant performance advantage compared to other high-end FPGA and software solutions:
- Stratix IV FPGAs and Quartus II software offer the highest performance in the industry.
- Advanced Place-and-Route Algorithms offer the fastest push-button results in the industry.
- Quartus II software's Design Space Explorer (PDF) script increases average design performance by 20 percent, automatically applying combinations of netlist optimizations and advanced Quartus II software compiler settings.
- Quartus II software's physical synthesis can re-wire logic connections, duplicate registers, and move registers to significantly improve overall circuit performance.
Only Parallel Development for FPGAs and HardCopy ASICs
Only Quartus II software provides a single methodology for developing your design for FPGAs and ASICs. By enabling compilation for HardCopy® ASICs, Quartus II software provides the only risk-free path to the benefits of FPGAs and the benefits of ASICs.
Getting Started with Stratix IV FPGAs and Quartus II Software
Stratix IV FPGAs are supported in Quartus II Subscription Edition software version 8.0 (or later). Download the Quartus II subscription edition software and start designing your Stratix IV FPGAs today with the included free 30-day trial. To purchase an Altera subscription package, contact your local distributor or sales representative.
