Stratix® GX FPGAs give system architects a low-risk path to 3.125-Gbps transceiver applications. Based on Altera's Stratix architecture, Stratix GX devices fuse the industry's fastest FPGA architecture with high-performance multi-gigabit transceiver technology.
System designs that require a low-risk cost-reduction path for high-volume production can migrate Stratix GX designs seamlessly to mask-programmed, pin-compatible HardCopy® Stratix GX devices. Because HardCopy Stratix GX devices preserve the high-density, high-performance architecture of Stratix GX FPGAs, including the 3.125-Gbps high-speed transceivers, no additional high-speed board design engineering is required when migrating from Stratix GX FPGAs to HardCopy Stratix GX devices.
Table 1 outlines the Stratix GX device family members and features. Table 2 shows an overview of Stratix GX device packaging and I/O pin counts. Table 3 shows the appropriate configuration devices to use for Stratix GX devices. Table 4 shows the industrial temperature support for Stratix GX devices.
| Table 1. Stratix GX FPGA Family Overview | |||||||
| Feature | EP1SGX10C | EP1SGX10D | EP1SGX25C | EP1SGX25D | EP1SGX25F | EP1SGX40D | EP1SGX40G |
|---|---|---|---|---|---|---|---|
| LEs | 10,570 | 10,570 | 25,660 | 25,660 | 25,660 | 41,250 | 41,250 |
| Full-Duplex Transceiver Channels | 4 | 8 | 4 | 8 | 16 | 8 | 20 |
| Source- Synchronous Channels |
22 | 22 | 39 | 39 | 39 | 45 | 45 |
| M512 RAM Blocks (512 Bits + Parity) | 94 | 94 | 224 | 224 | 224 | 384 | 384 |
| M4K RAM Blocks (4 Kbits + Parity) | 60 | 60 | 138 | 138 | 138 | 183 | 183 |
| M-RAM Blocks (512 Kbits + Parity) | 1 | 1 | 2 | 2 | 2 | 4 | 4 |
| Total RAM Bits | 920,448 | 920,448 | 1,944,576 | 1,944,576 | 1,944,576 | 3,423,744 | 3,423,744 |
| DSP Blocks | 6 | 6 | 10 | 10 | 10 | 14 | 14 |
| 9-Bit x 9-Bit Embedded Multipliers (1) | 48 | 48 | 80 | 80 | 80 | 112 | 112 |
| PLLs (2) | 4 | 4 | 4 | 4 | 4 | 8 | 8 |
| Availability | Buy Now | Buy Now | Buy Now | Buy Now | Buy Now | Buy Now | Buy Now |
- Total number of 9×9 multipliers. To obtain the total number of 18×18 multipliers per device, divide the total number of 9×9 multipliers by a factor of 2. To obtain the total number of 36×36 multipliers per device, divide the total number of 9×9 multipliers by a factor of 8.
- Includes both enhanced PLLs and fast PLLs.
| Table 2. Stratix GX Device Package and Maximum User I/O Pins | |||||||
| Package Size (mm x mm) |
EP1SGX10C | EP1SGX10D | EP1SGX25C | EP1SGX25D | EP1SGX25F | EP1SGX40D | EP1SGX40G |
|---|---|---|---|---|---|---|---|
| 672-Pin FineLine BGA® 27 x 27 |
330 | 330 | 426 | 426 | - | - | - |
| 1,020-Pin FineLine BGA 33 x 33 (1) |
- | - | - | 542 | 542 | 548 | 548 |
- The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock reference pins for high-speed I/O capability.
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