Today's high-speed applications need reliable data transfer technology that gets information from source to destination fast. To meet this need, Altera introduced the Stratix® GX FPGA, a powerful fusion of 3.1875-Gbps transceiver technology with the award winning Stratix FPGA architecture. The complete Stratix GX design package—including silicon, development platform, user guide, design guidelines, SerialLite protocol, and technical support—provides a low-risk path to 3.1875-Gbps transceiver applications.
Carrying forward the concept of integrated transceiver technology first brought to the FPGA market by Altera, Stratix GX devices include up to 20 full duplex transceiver channels, each capable of operating at up to 3.1875 Gbps per channel while consuming minimal power. Built on the Stratix architecture, Stratix GX devices offer the same features, including TriMatrix memory, digital signal processing (DSP) blocks, and advanced clock management circuitry for intensive data path processing functions. Stratix GX devices are ideal for implementing interface protocols such as SerialLite, 10 Gigabit Ethernet attachment unit interface (XAUI), or customized functions that require data rates up to 3.1875 Gbps.
Multi-Gigabit Design Made Easy
Multi-gigabit system design requires more than just a functional FPGA. Altera delivers a complete design platform that includes silicon, software, SerialLite protocol support, intellectual property (IP), a comprehensive support infrastructure, documentation, board design guidelines, product interoperability testing, and development kits and boards. This comprehensive platform ensures you have all the tools you need to create a working transceiver-based system, be it for backplane or chip-to-chip applications. Using these tools, you can eliminate potential issues that could arise during the design process and minimize implementation risks.
Stratix GX Gigabit Transceiver Blocks
Stratix GX devices feature multiple gigabit transceiver blocks, each with four full duplex channels. Using clock data recovery (CDR) technology, these channels serialize or deserialize data for transmission rates up to 3.1875 Gbps. Each channel features dedicated circuitry that implements various stages of the data recovery and transmission, decoding and encoding, and manipulation processes. A seamless interface with the programmable logic ensures reliable data transfer, maximized data throughput, and simplified timing analysis.
Gigabit transceiver block highlights include:
- Support for transceiver protocols including SerialLite, XAUI, SONET/SDH, Gigabit Ethernet, Fibre Channel, InfiniBand, Serial RapidIO®, PCI Express, SMPTE 292M, SFI-5, and SPI-5 protocols
- Low power consumption per channel (175 mW) and per gigabit transceiver block (450 mW)
- Programmable pre-emphasis, equalization, and differential output voltage settings
Dynamic Phase Alignment for Accelerated Source-Synchronous Signaling
Source-synchronous I/O channels capable of 1-Gbps performance balance data transfer through the device. These channels, located on the opposite side of the device from the transceiver blocks, enable users to move data on and off the device using the LVDS, HyperTransport, or LVPECL I/O standards across multiple channels. Each channel is equipped with embedded SERDES technology to simplify design implementation.
Recognizing the challenges you face when designing systems that transfer high-speed data without CDR technology, Altera incorporated the dynamic phase alignment (DPA) feature into Stratix GX devices. This feature dramatically simplifies printed circuit board (PCB) design, eliminating signal alignment issues introduced by skew-inducing effects when using source-synchronous signaling techniques. DPA eliminates timing issues that potentially could lead to initial product deployment delays. Using DPA, you can focus on system implementation and optimization rather than complex board design issues.
The Best Programmable Logic and Development Software
Stratix GX devices are based on the high-performance Stratix FPGA architecture and offer the same features:
- Abundant TriMatrix memory for on-chip storage
- Robust clock management and frequency synthesis using embedded phase-locked loops (PLLs) for managing on- and off-chip timing
- Fast external memory access with dedicated interface circuitry to DRAM and SRAM devices
- Embedded processor capability with the Nios® II embedded processor family
- Differential on-chip termination for moderate performance signals
- High-bandwidth DSP blocks for signal processing-intensive applications
- Remote system upgrade feature that ensures the reliable and safe deployment of system upgrades and bug fixes
System designs that require a low-risk cost-reduction path for high-volume production can migrate Stratix GX designs seamlessly to a mask-programmed, pin compatible HardCopy® Stratix GX ASIC. Since the HardCopy Stratix GX ASIC preserves the high-density, high-performance architecture of the Stratix GX FPGA, including the 3.1875 Gbps high-speed transceivers, no additional high-speed board design engineering will be required when creating a HardCopy Stratix GX ASIC.
The Stratix GX FPGA is supported in Quartus® II software and all major third-party synthesis and simulation tools, available today for implementing multi-gigabit designs. The devices are complemented by board-level simulation tools and Stratix GX FPGA-optimized intellectual property (IP).
- Complete Stratix GX Design Package
- SerialLite Protocol for Stratix GX devices
- Stratix GX Architecture
- Stratix GX Signal Integrity Center
- Stratix GX Source-Synchronous Signaling
- Stratix GX Source-Synchronous Protocols
- Stratix GX Applications
- Nios II embedded processor family
- Stratix & Stratix GX Device Architectural Differences
- Stratix GX Questions & Answers
- Performance in High-Density FPGAs
- Benchmarking Methodology