DRAM Support in Stratix Devices

Dynamic random access memory (DRAM) is an asynchronous memory technology based on small capacitor cell memory arrays that require repeated refresh cycles during operation. Although using refresh cycles adds memory controller design complexity, the small capacitor cell size translates to denser memory arrays for increased storage capacity at lower cost.

Altera^® Stratix™ devices support interfaces with three types of high-speed synchronous DRAM (SDRAM) devices: single data rate (SDR SDRAM), double data rate (DDR SDRAM), and fast-cycle (FCRAM) with clock speeds of up to 200 MHz.

SDRAM Devices

SDRAM devices were defined by the JEDEC to address the performance limitations of older DRAM architectures such as fast page mode (FPM) and extended data out (EDO) devices. SDRAM devices are capable of faster speeds because, unlike FPM and EDO memory devices, they synchronize memory transactions to the positive edge of a system clock. In the older FPM and EDO devices, a memory access is executed a certain amount of time after the assertion of a control signal, depending on the characteristic propagation delays of the device.

Several factors contribute to greater overall memory bandwidth in SDRAM devices:

Fast system clock speeds
Burst capabilities that allow multiple column accesses for a single read or write row address
Pre-charging of memory array partitions to reduce reactivation latency

An SDRAM functional block diagram is shown in Figure 1.

Figure 1: SDRAM Functional Block Diagram (1)

Figure 1: SDRAM Functional Block Diagram

Note:

Source: Texas Instruments, Inc.

DDR SDRAM Devices

DDR SDRAM devices are an evolutionary variation of SDR DRAM devices, achieved by permitting transactions on both the rising and falling edges of the clock to effectively double data transfer rates. A strobe-based data bus accounts for variations between clock and data (DQ) signals due to changes in temperature, voltage, or loading. The data strobe (DQS) bidirectional signal acts as a reference signal for memory device writes and memory controller reads. Since the DQ and DQS signals are routed adjacent to each other during printed circuit board (PCB) design, skew is minimized and data can be latched correctly. DDR SDRAM devices use the SSTL-2 Class II I/O standard.

Memory Solutions Center - DDR SDRAM provides access to technical documentation, intellectual property (IP) cores and reference designs, software and tool support, demo boards, characterization report, presentations, and articles on DDR SDRAM.

DDR FCRAM Devices

DDR FCRAM devices aim to bridge the performance gap between faster SRAM devices and DRAM devices. Developed by Fujitsu Microelectronics, DDR FCRAM devices are based on a DRAM core architecture and have a DDR interface. Proprietary pipeline and hidden pre-charge operations significantly reduce random cycle access times. DDR FCRAM devices also consume less power due to memory core segmentation techniques.

Applications

SDRAM devices are most commonly used in low-cost applications that require access to a large amount of memory at high speeds, such as digital access cards in voice over Internet protocol (VoIP) applications. An example is illustrated in Figure 2.

Figure 2: Digital Access Card

Figure 2: Digital Access Card

Intellectual Property (IP)

Altera offers fully customizable IP megafunction controller cores: