from Altera
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Features
- 800 MHz dual-core processor supporting symmetric and asymmetric multiprocessing
- Each processor includes the following:
- High-efficiency, dual-issue superscalar pipeline (2.5 MIPS* per MHz)
- NEONTM media processing engine for media and signal processing acceleration
- Single- and double-precision floating-point unit
- 32 KB instruction and 32 KB data caches
- Cache coherence for enhanced inter-processor communication
- Memory Management Unit with TrustZone® security technology
- Thumb®-2 technology for enhanced code density, performance, and power efficiency
- Jazelle® architecture extensions for accelerating Java Virtual Machine
- Program Trace Macrocell for full visibility of processor instruction flow
- Shared 512 KB, 8-way associative L2 cache, lockable by way, line, or master
- Acceleration coherency port that extends coherent memory access beyond the CPUs
- Generic interrupt controller
- 32 bit general purpose timer
- Watchdog timer
- Available in Altera® Arria® V SoCs and Cyclone® V SoCs
* Dhrystones 2.1 benchmark
Block Diagram
Description
A dual-core ARM® CortexTM-A9 MPCoreTM applications-class processor is integrated as a hard intellectual property (IP) component in Altera's Arria V SoCs and Cyclone V SoCs. Optimized for maximum system performance, the ARM Cortex-A9 processor leverages best-in-class development tools and operating system support from the vast array of ARM ecosystem partners.
HPS
The ARM Cortex-A9 processor is combined with a rich set of embedded peripherals, interfaces, and on-chip memories to create a complete hard processor system (HPS). The high-bandwidth on-chip backbone connecting the HPS and FPGA fabric provides over 100 Gbps peak bandwidth, ideal for sharing data between the ARM processor and hardware accelerators within the FPGA fabric.
