Based on the ARM® Development Studio 5 (DS-5™) Toolkit, the ARM DS-5 Altera® Edition Toolkit is a device-specific, exclusive offering that removes the debugging barrier in SoC devices by seamlessly extending embedded debugging capabilities across the CPU-FPGA boundary. These FPGA-adaptive debugging capabilities increase productivity by giving users an unmatched level of visibility and control over the entire device.
The ARM DS-5 Altera Edition Toolkit is part of the Altera SoC Embedded Design Suite (EDS) and is shipped by Altera through an exclusive agreement.
Comprehensive Development Environment
Delivered as a part of the Altera SoC EDS, the ARM DS-5 Altera Edition Toolkit provides a comprehensive set of embedded development tools for the Altera SoC devices. Key features include:
- Support for board bring-up, driver development, operating system (OS) porting, bare-metal, and Linux application development
- Application build support, including a Yocto plug-in to support building Linux-based applications
- Development and debugging support for systems running in symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) modes
- Most advanced multicore debugging capabilities for the ARM architecture and FPGA-adaptive debugging for Altera SoC devices
- Simultaneous debug and trace connection for ARM Cortex™-A9 processors as well as any custom cores with ARM CoreSight™ trace macrocells synthesized on the FPGA fabric
- ARM Streamline Performance Analyzer with performance counters from the SoC and FPGA domains to enable full system-level analysis
Figure 1. ARM DS-5 Toolkit Enables Debugging of Linux Applications
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Every SoC-based system design is unique due to the customized logic programmed into the FPGA. In order to debug the system effectively, the ARM DS-5 Altera Edition Toolkit dynamically adapts to your configuration. It unifies all software debugging information from the CPU and FPGA domains and presents them in an organized fashion within the standard DS-5 user interface. Altera and ARM developed the toolkit to give you an unprecedented level of debugging visibility and control that delivers substantial productivity gains.
The toolkit displays pre-configured CPU subsystem peripheral register views and enables automatic generation of registers views for peripherals in the FPGA fabric. All register views are self-documenting and organized by peripherals, registers, and bit-fields.
Working with the Altera SignalTap™ II Logic Analyzer, the toolkit provides advanced, signal-level hardware cross triggering between the CPU and FPGA domains. Using this capability, the software and FPGA designers can analyze the captured trace and co-debug across hardware-to-software boundary.
Figure 2. A Trigger Point Set in SignalTap II Logic Analyzer Starts Software Trace Collection
Compatible with Altera Tools and Development Kits
For your convenience, the toolkit and other Altera JTAG-based tools can be connected to the Altera SoC board via a single Altera USB-Blaster™ cable. The toolkit also can program the flash ROM on all Altera SoC development kits and compatible boards.