Altera's portfolio of embedded soft processors lets you take full advantage of the inherent parallelism of FPGAs to achieve high levels of system performance. Multiple processors can execute code simultaneously while hardware accelerators can offload compute-intensive algorithms at the same time. Upgrade your embedded system's performance at any stage of the product life cycle without the need to redesign the board or develop hand-optimized assembly code.
There are several ways to upgrade system performance:
- Soft processor cores
- Custom instructions
- Configurable caches and tightly coupled memories
- Multiprocessor systems
- High-bandwidth system interconnect
If you're using our Nios® II processors, you can choose from three code-compatible soft processor cores (see Figure 1):
- One optimized for maximum system performance
- One optimized for minimum logic usage
- One that strikes a balance between maximum system performance and minimum logic usage
You can easily configure these cores with features such as multipliers, user-specified cache memories, custom instructions, hardware debug logic, and more to adapt to your specific performance needs.
Figure 1. Nios II Processor Core Performance
- Learn more about the Nios II family of processor cores
- Learn more about processor configuration options (PDF)
Other soft processors in our embedded portfolio include:
- The MP32 processor, the industry's first 100 percent MIPS®-compatible soft processor
- The ARM® CortexTM-M1 processor, a three-stage 32-bit ARM Cortex processor
- The Freescale ColdFire V1 processor, which has a fully synthesizable core and variable-length RISC 16-bit, 32-bit, and 48-bit instructions
- The Intel® Atom® E6x5C processor, which combines the Intel Atom processor E6xx with an Altera® FPGA on a multi-chip package
Accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. You can add up to 256 custom instructions to each processor core to reduce the number of clock cycles required for numeric calculations, bit manipulation, and other complex processing algorithms (see Figure 2).
Figure 2. Custom Instruction Logic
Adjust the size of the processor instruction or data cache to meet the performance needs of your application. For fast access to frequently used routines in the Nios II processor, add up to four tightly coupled memories that provide cache-like access without the penalty of cache misses.
- Read about cache and tightly coupled memory in the Nios II Software Developer's Handbook (PDF)
- Download the Using Nios II Tightly Coupled Memory Tutorial (PDF)
Altera provides a broad portfolio of embedded processors, consisting of soft processor cores, for use in any FPGA and specific FPGA families with integrated dual-core hard processor systems.
Use multiple soft-core processors to scale your system's performance or to partition software applications into smaller, simpler tasks that are easier to write, debug, and maintain. The Nios II Embedded Design Suite (EDS) and tools from industry-leading embedded software providers support developing and debugging multiprocessor applications. Nios II processors, combined with high-density devices such as the Stratix® family of FPGAs and HardCopy® ASICs, are ideal platforms for creating high-performance multiprocessor systems (see Figure 4).
Figure 4. Multiprocessor Example
- Learn how to build a multiprocessor system using the Nios II processor (PDF)
- Learn more about Altera's embedded software partners
Altera’s dual-core ARM® Cortex-A9 MPCoreTM SoC FPGAs integrate hard processor systems that let you partition software tasks across two applications-class embedded processors in symmetric, or asymmetric, multiprocessing operation.
Altera's Qsys system-integration tool, available in later versions of Quartus® II design software, lets you generate high-throughput systems that take advantage of the inherent parallelism of FPGAs. The system interconnect fabric is fully switched, in that dedicated connections between master and slave components allow multiple simultaneous transactions without the arbitration stalls found in traditional bus architectures. Unburden your processor by using intelligent direct memory access (DMA) channels.
- Learn more about system interconnect fabric features
- Avalon® Memory-Mapped Interface Specification (PDF)
- Learn more about the DMA controller core (PDF)
- Protect your software investment from processor obsolescence
- Improve your productivity
- Reduce your system costs
- Establish a competitive advantage with flexible hardware