News and Events

Introducing the SoC FPGA – Your Customizable ARM Processor-Based SoC

SoC FPGAs let you reduce system power, system cost, and board space by integrating a hard processor system (HPS) – consisting of processors, peripherals, and memory controller – with the FPGA fabric using a high-bandwidth interconnect backbone. The combination of the HPS with Altera's 28-nm low-power FPGA fabric provide the performance and software ecosystem of an applications-class ARM^® processor with the flexibility of programmable logic.

The first two members, based on Arria^® V and Cyclone^® V FPGAs, include a dual-core ARM Cortex^TM-A9 MPCore^TM processor, running at up to 800 MHz, with a rich set of embedded peripherals including Ethernet, USB, flash memory, SDRAM controller, and more. Multiple ARM AMBA^® AXI^TM bus bridges provide over 100 Gbps peak throughput between the processors and custom logic in the FPGA. Arria V SoC and Cyclone V SoC FPGAs leverage the advanced 28-nm low-power programmable fabric maximized for logic efficiency, allowing you to implement your design with the fewest resources and lowest possible power.

The ARM embedded software ecosystem offers the broadest range of operating system, middleware, and development tools available from the top embedded software providers worldwide. Get started developing software today with Altera's SoC FPGA Virtual Target development environment.

Learn more about the SoC FPGAs:

Begin Your Embedded Development with the Nios II Processor on the Arria V FPGA Platform Today!

The Altera^® Nios^® II processor, the industry's most versatile soft processor for microcontroller, real-time, applications, and safety-critical processing is now available for development with Altera's new Arria V FPGAs. Use the Nios II Embedded Design Suite (EDS), Altera's portfolio of embedded intellectual property (IP) cores, and Qsys system integration tool to begin developing your Arria V FPGA-based embedded solution today!

MP32 Processor Brings MIPS Ecosystem to Programmable Logic Applications

Altera, MIPS^® Technologies, and System Level Solutions (SLS) Corp. have partnered to provide the MP32 processor for Altera's FPGAs and HardCopy^® ASICs. The MP32 processor brings the expansive MIPS ecosystem of software and tools to programmable logic applications. It is the industry's first 100 percent MIPS32 2.0 architecture-compatible soft processor and it also supports the popular VxWorks operating system (OS). When combined with Altera's broad portfolio of embedded IP cores, innovative FPGA design tools, and the industry's leading portfolio of programmable logic devices, the MP32 processor is ideal for the development of flexible, single-chip solutions for networking, video, and digital signal processing.

The processor is backed by Qsys, a rapid system design flow. With the VxWorks real-time OS, you can reuse legacy software application code with the MP32 processor. You can also reuse IP cores offered by Altera and SLS, and include your own.

The MP32 processor is available now from SLS. When targeting Altera's FPGAs, the MP32 processor is offered royalty free and sold on an unlimited number of cores and perpetual-use basis.

For more information, visit the MP32 processor web page.

Experience the Next-Generation System Integration Capabilities of Qsys

With increasing FPGA densities and system complexity, the need for increased system performance and efficient ways to design embedded systems becomes paramount. Qsys, the next-generation SOPC Builder system integration tool, offers several key enhancements for increasing performance, managing large systems, and enabling faster system design through design reuse.

Features and Benefits

Higher performance: Qsys automatically generates new and improved system interconnect logic. The resulting interconnect performance achieved is up to 2X what SOPC Builder offers. Furthermore, system designers can now trade off latency (important for fast access in control paths, such as access from processor to memory and access to look-up tables for on-chip and off-chip memory) with f_MAX (important for achieving high throughput for point-to-point datapath functions, accelerators, and coprocessors), resulting in increased overall system performance.
Hierarchical design flow (system within a system): As embedded systems get larger, the ability to design a system and export it as a subcomponent within a larger system becomes increasingly important. Qsys supports such a hierarchical design flow where designers can more easily manage each subsystem, raise the level of abstraction, and benefit from the reuse of tested and verified subsystems.

Getting Started with Qsys

The following resources are available to get started with using the Qsys system integration tool for your embedded system development:

Take the training course, System Integration with Qsys
Find out how you can migrate your application from SOPC Builder to Qsys by reading the application note, AN 632: SOPC Builder to Qsys Migration Guidelines (PDF)
For more information visit the Qsys web page

Don't Forget to Renew your Nios II Processor IP License for v11.1

When you purchase or renew your Nios II IP core license or Embedded IP Suite—a value bundle of Altera's most popular embedded IP cores—you are entitled to support for updates to embedded tools included in the latest Nios II Embedded Design Suite (EDS). You are also entitled to enhancements to the Nios II processor. Contact your local Altera sales representative or distributor to place your order.

Nios II EDS Installation

In the Altera Complete Design Suite v11.1, the Nios II EDS is included with the Quartus^® II software v11.1 download so no separate download or installation is required.

The Nios II EDS includes the Nios II Software Build Tools (SBT) for Eclipse, the next generation of the Nios II Integrated Development Environment (IDE). The Nios II IDE will continue to ship, and will be available for download as a stand-alone installation. You can find instructions on how to convert your Nios II IDE project to the new Nios II SBT for Eclipse in Appendix A. Using the Nios II Integrated Development Environment (PDF).

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