Updates for Nios® II Processor in the Quartus® II v13.1 Software Tool
- GCC upgrade to v4.7.3
The v13.1 Nios II Embedded Development Suite (EDS)/Software Built Tools (SBT) supports v4.7.3 version of GCC for smaller code size and compatibility with the latest versions of currently available from rocketboards.org.
- Enhanced floating-point custom instruction support
Get the option to select a new floating-point custom instruction set component in the Qsys Tool. The component has one combinatorial custom instruction and one multi-cycle custom instruction. The combinatorial custom instruction implements comparison, minimum, maximum, negate, and absolute operations. The multi-cycle custom instruction implements add, subtract, multiply, divide, square root, and conversion operations. These are binary compatible with the previous custom instructions, but offer superior performance (fewer cycles operation).
- Error correction code (ECC) support
The optional ECC in the Nios II configuration wizard enables ECC protection on the RAMs inside the processor core and the instruction cache (data cache with ECC enabled is currently not supported). Single-bit soft errors are corrected and dual-bit soft errors cause either an instruction cache flush or processor exception. Only available on the Nios II /f core without data cache.
- RTL Nios II processor trace simulation support
This feature enables recording and time-stamping of Nios II processor instruction execution during register transfer language (RTL) simulation in ModelSim® Altera software edition of events such as instruction execution and address, data address and value, interrupts, and control register changes.The time-stamp allows the developer to align hardware simulation data with software execution.
Breakthrough Advantages with Generation 10 FPGAs and SoCs
Altera introduced its Generation 10 FPGAs and SoCs, offering system developers breakthrough levels of performance and power efficiencies. Generation 10 devices are optimized based on process technology and architecture to deliver the industry's highest performance and highest levels of system integration at the lowest power. Initial Generation 10 families include Arria® 10 and Stratix® 10 FPGAs and SoCs with embedded processors. Generation 10 devices leverage the most advanced process technologies in the industry, including Intel's 14 nm Tri-Gate process and TSMC's 20 nm process.
First FPGA-Adaptive DS-5 Toolkit Removes Debugging Barrier in SoC Devices
Altera and ARM have jointly developed the first FPGA-adaptive, unified debugger for Altera’s family of SoC devices. The ARM Development Suite (DS-5) Toolkit Altera Edition removes the debugging barrier between a CPU subsystem and an on-chip FPGA, giving you an unprecedented level of visibility and control through a common, familiar software debugging interface. Watch video.
Arria V and Cyclone V SoC Development with ACDS v13.0
Begin your system and intellectual property (IP) development by downloading Quartus® II software v13.0, which includes:
Cyclone V SoC
Arria V SoC
Nios II Design Example for Cyclone V GX FPGA Development Kit Now Available
The Cyclone V GX FPGA Development Kit is now shipping and includes a pre-packaged Nios II processor design example. This design example entitled "Board Update Portal", comprising a Nios II processor system with Ethernet MAC, runs a HTML server software application and is a great way to get started with your Nios II system development.
- Purchase a Cyclone V GX FPGA development kit today
- Nios II processor "Board Update Portal" example designs are also available for Arria V GX FPGA Development Kit, Arria V GX FPGA Starter Kit, and Stratix V GX FPGA Development Kit
Impulse C Software-To-Hardware Compiler for Nios II Processsor
Impulse Accelerated Technologies, a leader in software-to-hardware technologies is offering the Impulse CodeveloperTM, which includes the Impulse CTM software-to-hardware compiler for C based IP and software acceleration for the Nios II Processor. Using available Nios II Platform Support Packages you can develop Avalon® Memory-Mapped (Avalon-MM) hardware IP components and simply add them to your Qsys project. Impulse Accelerated Technologies is also offering special pricing for Altera customers.
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