Altera specifically designed the Nios® II/e "economy" processor core to use the fewest FPGA logic and memory resources. It is now offered free, no license required, with Quartus® II software version 9.1 and later. The Nios II/e core has higher performance but is in the same cost class as a typical 8051 architecture, achieving over 30 DMIPS at up to 200 MHz, and using fewer than 700 logic elements (LEs).
The free Nios II/e core features:
- Up to 2 GB of external address space
- JTAG debug module
- Complete systems in fewer than 700 LEs
- Optional debug enhancements
- Up to 256 custom instructions
The Nios II/e core is optimal for cost-sensitive applications, such as those found in the automotive, industrial, and consumer markets. This core is often paired with Altera's low-cost FPGAs.