Altera specifically designed the Nios® II/s "standard" processor core to implement a small processor core without a significant trade-off in software performance. The Nios II/s core is optimal for cost-sensitive, medium-performance applications, including those with large amounts of code and/or data, such as systems running a full-featured operating system.
The Nios II/s core features:
- Instruction cache
- Up to 2 GB of external address space
- Optional tightly coupled memory for instructions
- 5-stage pipeline
- Static branch prediction
- Hardware multiply, divide, and shift options
- Up to 256 custom instructions
- JTAG debug module
- Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
The Nios II/s core provides additional functionality and performance when targeting Altera® device families with digital signal processing (DSP) blocks. In this case, the Nios II/s core provides hardware multiply circuitry that achieves 3-cycle multiplication operations. The multiply unit also functions as a barrel shifter.