Altera offers a variety of embedded training resources including online training, instructor-led courses, webcasts, tutorials, and online demonstrations to sharpen your competitive edge.
Not sure which courses to take? Here are suggested curricula to get you up to speed as quickly as possible.
| Title | Description |
|---|---|
| Online Training | |
| ARM SoC FPGA | |
| SoC FPGA Hardware Overview (Part 1) | This online training describes the Cyclone® V and Arria® V SoC FPGA hardware, and in particular, the hard processor system (HPS). The online training includes information about the master programming unit (MPU) subsystem, including the ARM® Cortex™-A9 processor core, the AMBA® AXI™ bridges, the Level 3 and Level 4 interconnects, and the main memory that is included in the HPS. Course Length: 1 hour |
| SoC FPGA Hardware Overview (Part 2) | This online training describes about the Cyclone V and Arria V SoC FPGA hardware, and in particular, the HPS. The online training includes information about the peripherals included in the HPS. You will learn about system management, non-volatile storage, interface protocols, general purpose peripherals, and debugging techniques. Course Length: 30 minutes |
| Nios II Processor | |
| Developing Software for Embedded Systems on FPGAs | This online training describes how to develop software for embedded systems on FPGAs. FPGAs are becoming more common in embedded design. See how easy it is to develop embedded system software for FPGAs using the popular Nios® II soft processor. Course Length: 6 minutes |
| Developing Software for the Nios II Processor: Nios II Software Build Tools for Eclipse | This online training describes about the Nios II Software Build Tools for Eclipse, a comprehensive collection of tools for Nios II software development including compiling, editing, debugging, and flash programming. This course is an introduction on how to use these tools. Course Length: 30 minutes |
Developing Software for the Nios II Processor: |
This online training describes about Altera’s embedded software development tools in detail. You will find out what operating systems, middleware, and software packages are available for the Nios II processor. The course includes helpful resources and support information. Course Length: 30 minutes |
| Developing Software for the Nios II Processor: Design Flow |
This online training describes about Altera’s embedded development flow for Nios II processor-based systems. This online training covers the FPGA hardware design flow, the Nios II software development flow, and the flash programmer flow. Course Length: 30 minutes |
| Nios II Software Build Tools For Eclipse and BSP Editor | This online training describes about the Nios II Software Build Tools for Eclipse. You will learn how to upgrade Nios II Integrated Development Environment (IDE) projects and use the Nios II BSP Editor—a powerful feature that enables fine control over software build options. This online training was last updated for Quartus II v10.0. Course Length: 30 minutes |
| Developing Software for the Nios II Processor: HAL Primer |
This online training introduces the fundamental concepts of the Nios II Hardware Abstraction Layer (HAL) and shows the various HAL resources that are provided to accelerate software development for the Nios II processor. Course Length: 30 minutes |
| Developing Software for the Nios II Processor: Debug Primer |
This online training describes the basic principles of debugging software for the Nios II processor. You will be introduced to the fundamentals of the Nios II IDE debugger and its features. You will see a demo on how to set up a debug session in the Nios II IDE and debug a small application. Course Length: 30 minutes |
| Developing Software for the Nios II Processor: Software Build Flow (Part 1) |
This online training describes the features of the Nios II software build flow. You will view two demos on how to build and run a “Hello World” application from the command shell. The demos also show you how to import a software build flow project into the Nios II EDS for debugging. Course Length: 30 minutes |
| Developing Software for the Nios II Processor: Software Build Flow (Part 2) |
This online training shows you how to build complex board support packages (BSPs) for your software projects using the powerful BSP generation commands. You will watch a demo that shows you how to generate a BSP and add an operating system and a network stack to it. Course Length: 30 minutes |
| Using the Nios II Processor | This online training introduces you to the soft core Nios II embedded processor, the system on a programmable chip (SOPC) Builder tool, and the Nios II IDE. You will learn how to utilize SOPC Builder to easily develop and configure fully customized Nios II processor-based hardware systems at the touch of a button. Course Length: 1 to 2 hours |
| Nios II Floating-Point Custom Instructions | This online training introduces you to the features of Nios II processor floating-point custom instructions and shows you how to add them to the Nios II processor. This online training also includes information about writing software application code that utilizes these floating-point custom instructions. Course Length: 30 minutes |
| System Integration and Hardware Development | |
| Introduction to Qsys | This online training introduces you to Qsys; a tool to integrate embedded processors with intellectual property (IP) cores and your custom IP. Learn the benefits of system integration with Qsys, system debugging with system console, and functional simulation using the bus functional model (BFM). Course Length: 1.5 hours |
| Advanced System Design Using Qsys | This online training describes how Qsys has the ability to increase system performance or reduce system power using control and data plane partitioning, and system topology management. You will also learn the tips and tricks to optimize your Qsys system. Course Length: 1 hour |
| VHDL Basics | This online training provides an overview of the VHDL language and its usage in programmable logic design. While the emphasis is on the synthesis constructs of VHDL, you will also learn about some simulation constructs. You will gain a basic understanding of VHDL that enables you to begin creating your design. Course Length: 1.5 hours |
| Instructor-Led Training | |
| Developing Software for the Nios II Processor | This training is targeted for software engineers. This training teaches you how to develop and run embedded software for the Nios II processor in the Nios II IDE. You will also be exposed to a few basic concepts including how a Nios II processor is configured and integrated into an Altera® FPGA using Quartus® II software and SOPC Builder design tools. Course Length: 2 days |
| Designing with the Nios II Processor | This training teaches you how to embed a Nios II 32-bit microprocessor soft core into your FPGA design. Learn how the software build flow is incorporated into the hardware flow, perform debug and bring up of a design, simulate your Nios II-based design in the ModelSim®-Altera software, and create custom instructions to perform hardware acceleration of software functions. This training enables you to immediately start using the Nios II processor v11.1 in your designs or on a development kit. Course Length: 1 day |
| Introduction to the Qsys System Integration Tool | This training teaches you how to quickly build designs for Altera FPGAs using Altera’s Qsys system-level integration tool. Learn how to quickly integrate IP and custom logic into a system and how to optimize designs for performance. This training enables you to dive deeply into the Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interfaces with significant hands-on tool usage as well as system and custom HDL component design. Course Length: 1 day |
| Advanced Qsys System Integration Tool Methodologies | This training teaches you about the advanced features of Altera’s Qsys system level integration tool and enables you to expand your knowledge of the Quartus II FPGA design software v11.1. You will learn how to simulate Qsys systems in the ModelSim-Altera software using Avalon BFMs, exercise and monitor system behavior with the System Console, and build hierarchical Qsys systems. This training provides a significant hands-on component, where you will gain exposure to tool usage and system design. Course Length: 1 day |
| Online Demonstrations | |
| Nios II Processor Hardware Development Flow | This online demonstration includes the following topics:
|
| Nios II Software Development Flow | This online demonstration includes the following topics:
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| Programming Flash | This online demonstration shows you how the Nios II flash programmer programs data into a flash memory device connected to an Altera FPGA. The flash programmer sends file contents over an Altera download cable to a Nios II processor system running on the FPGA. |
| Tutorials | |
| These tutorials provide you with step-by-step instructions and walk you through simple design examples. | |
| This tutorial teaches you how to build a single design with multiple Nios II processors and run the software. | |
Using Tightly Coupled Memory with the Nios II Processor Tutorial (PDF) |
This tutorial teaches you how to boost real time system performance using tightly coupled memory with the Nios II processor to store critical code or data for low-latency access. |
