Release Notes For ModelSim Altera 10.0c Sep 21 2011 Copyright 1991-2011 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation and licensing see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [3]http://www.model.com/support/default.asp or find them in the installed modeltech tree in /docs/rlsnotes How to get Support ModelSim Altera is supported by Altera Corporation * World-Wide-Web Support [4]http://www.altera.com/mySupport _______________________________________________________________________ Index to Release Notes [5]Key Information [6]User Interface Defects Repaired in 10.0c [7]Verilog Defects Repaired in 10.0c [8]PLI Defects Repaired in 10.0c [9]VHDL Defects Repaired in 10.0c [10]FLI Defects Repaired in 10.0c [11]VITAL Defects Repaired in 10.0c [12]SystemC Defects Repaired in 10.0c [13]Assertion Defects Repaired in 10.0c [14]Mixed Language Defects Repaired in 10.0c [15]General Defects Repaired in 10.0c [16]Known Defects in 10.0c [17]Product Changes to 10.0c [18]New Features Added to 10.0c _______________________________________________________________________ Key Information * The following lists the supported platforms: + win32aloem - Windows XP, Vista, Windows 7 + sunos5aloem - Solaris 10 (Starting 10.1 release, support for solaris will be discontinued.) + hp700aloem - HP-UX 11 + linuxaloem - RedHat 9 and higher, RedHat Enterprise Linux 3, 4 and 5, SUSE Linux Enterprise Server 9.0, 9.1 and 10. * The following platform will be discontinued as of the 6.3 release: + HPUX Platform - hp700aloem _______________________________________________________________________ User Interface Defects Repaired in 10.0c * Closing List window while actively updating causes crash. This issue is now fixed. * "see" command does not work after dofile error. This issue is now fixed. * Add signals to wave window which has with a fixed point radix causes a crash. This issue is now fixed. * When a design is loaded from the command line, the Modelsim GUI begins by loading the NoDesign layout and after the arguments are processed, the Simulate, Coverage or user defined layout is then loaded. If the NoDesign layout has many undocked windows, an error could occur during transition between these two layouts. The issue is difficult to reproduce as it is affected by computer performance as well as the number and type of undocked windows. The error message would look something like can't read itk_component(tbf21): no such element in array. The issue has been resolved. * When a design is loaded from the command line, the modelsim gui begins by loading the NoDesign layout and after the arguments are processed, the Simulate, Coverage or user defined layout is then loaded. If the NoDesign layout has many undocked windows, an error could occur during transition between these two layouts. The issue is difficult to reproduce as it is effected by computer performance as well as the number and type of undocked windows. The error message would look something like can't read itk_component(tbf21): no such element in array. The issue has been resolved. * In VRM, if a regression run is started at the same time that the GUI is launched (ie: "vrun -gui nightly", where "nightly" is the name of a Runnable), both the regression and the GUI would launch as expected but the status of the regression run would not be reflected in the GUI window. The workaround is to use the "Open Existing Regression" menu item to re-attach to the running regression. * When viewing a zoomed out, long run, if an composite signal was expanded the display would become very slow. The error has been corrected. * When using wlfman to filter or optimize wlf files, the file could take an excessive time to load if the signals contain many aliases to other signals. The error has been corrected. * When using wlfman to filter or optmize wlf files, the file could take an excessive time to load if the signals contain many aliases to other signals. The error has been corrected. * If a user specifies a nonexistent instance path in +acc option of vopt, vopt now gives warning instead of error. * In some cases, Source Annotation did not work after design recompiled and restarted in vopt mode. This issue has been fixed. * Dataflow window now correctly represents concatenation of signals in hiconn of port connection. _______________________________________________________________________ Verilog Defects Repaired in 10.0c * The incorrect constraint_mode value displayed as the name of the constraint is now hidden. * The incorrect constraint_mode value displayed as the name of the contraint is now hidden. * Fixed out of bound indexed array call to rand_mode. * A concatenation on the lhs of an assignment produced incorrect results in some very unusual cases. * Errors while using the $fdisplay() system task caused the simulation kernel to crash. * Vopt would sometimes generate an error like the following when complex wire types were declared in a SystemVerilog package: # ** Error: test.sv(34): Internal error: ../../../src/vlog/vgencode.c(51) loc != NULL * Vsim sometimes reported an internal error like the following in vopt mode: # ** INTERNAL ERROR: (vsim-8603) Package 'pkg1' has exported 6 items, but 7 items were expected. * If a process was blocked waiting for semaphore::get() to return and that process was disabled, it could corrupt memory in some cases causing unpredictable errors. * Fixed a couple of vopt internal errors related to module inlining in a System Verilog design. * Support added for 1800-2009 LRM section 3.14.2.2 timeunit with optional second argument. Example: timeunit 100ps / 10fs; * In certain cases, use of a $display system task in a gate-level cell could result in a crash or fail to display. * DPI import function/task formal with const ref port and open array type triggered compilation error. * Added a warning message when an optimized cell port is logged in the presences of v2k style interconnect delay describing that the hiconn is logged. * An erroneous error was printed in -novopt flow for an exported task: (vsim-3787) tb.sv(31): Exported task '_if.get' arguments don't match those of export/extern task in interface * Bind statements inside compilation unit scope would sometimes throw an unjustified 'already declared in scope' error in vopt. The error would go away if these statements were moved inside a wrapper module. This has been fixed. * A bind statement that uses parameters defined in a package as actuals would result in an incorrect 'object not found error' in vopt if the package was compiled in a library which is not included in bind's target module, but passed to vopt through -L command line option. This has been fixed. * Fixed crash involving referencing an interface port through a virtual interface. * Handle .* in bind where the actual module has duplicate ports. We previously printed an error. * In some cases, arguments to automatic task and function calls would incorrectly handle sign-extension or bit-length extension when the type of the actual was different than the type of the formal. * A force statement produced incorrect results when forcing a part-select of a variable where the part-select is wider than 8 bits. * Verilog parameter was not assigned value from vsim -g option even though the parameter did not receive explicit value in instantiation or via defparam, however other parameters were initiated using named override during the instantiation. This is now fixed. * A bit-select expression when passed as first argument to $size array query function, was flagged as an error "Invalid argument in array querying function.". This is now fixed. * In some cases, a concatenation expression, when passed as an argument to an external task, was incorrectly resulting in a VSIM error like: Error: (vsim-3047) top_hdl.sv(20): actual value for formal 'formal1' of 'mytask' must be assignable. This is now fixed. * Overriding a struct parameter with expression propagated incorrect parameter value with vopt. This has been fixed. * An Enum Declaration inside a generate loop, with an assignment to same could result in an error with vopt. * Applying a Verilog configuration with an instance use clause incorrectly modified the design IDL for a user instance by modifying the user_name attribute, causing all sibling instances to be rebound when only some instances were intended to be rebound by the configuration. This fix ensures that the user_name attribute is not permanently modified by the application of the use clause of a configuration. _______________________________________________________________________ PLI Defects Repaired in 10.0c * Memory allocated by acc_collect was freed on a call to acc_close rather than acc_free. * Some combinations of PLI functionality and the vsim -load_elab switch would not work together. * Some combinations of PLI functionality and vsim's -load_elab switch would not work together. _______________________________________________________________________ VHDL Defects Repaired in 10.0c * Optimization with vopt in the 3-step flow, or implicitly in the 2-step flow, could fail with an error similar to the following: ** Error: near "/": expecting STRING or IDENTIFIER or << This could happen in a design where vopt is invoked with a -L switch containing a directory path with "/" characters, and the design contains a configuration of an instantiation statement whose bound design unit exists in the library described with the -L switch. * Starting in this release the behavior of out mode variable parameter of array and record types can be modified. In previous releases, these type of parameter were not initialized to the default value of type when entering a subprogram. Therefore if all elements of an array or record (composite types) were not assigned to in the subprogram the previous values of actual were retained. In this release there is now an option -initoutcompositeparam that forces the out mode variable parameters to their default initial value when entering the subprogram. Use of this switch can change the behavior of a design in two cases. The first is that all elements of the out parameter are not assigned to in the subprogram, the actual value is no longer retained. The second case is if the actual associated with a composite out parameter is also associated with a composite in parameter. Because composites are passed by reference the initialization of the out parameter changes the value of the actual immediately along with the in parameter. * Starting in this release the behavior of out mode variable parameter of array and record types can be modified. In previous releases, these type of parameter were not initialized to the default value of type when entering a subprogram. Therefore if all elements of an array or record ( composite types) were not assigned to in the subprogram the previous values of actual were retained. In this release there is now an option -initoutcompositeparam that forces the out mode variable parameters to their default initial value when entering the subprogram. Use of this switch can change the behavior of a design in two cases. The first is that all elements of the out parameter are not assigned to in the subprogram, the actual value is no longer retained. The second case is if the actual associated with a composite out parameter is also associated with a composite in parameter. Because composites are passed by reference the initialization of the out parameter changes the value of the actual immediately along with the in parameter. * A package instantiation containing a static-sized array in the generic map could cause the compiler to issue an internal error. * If SDF annotation is present, impure function could be called multiple times at elaboration time resulting in errors. * If a design containing VHDL configurations that the same configurations specify multiple block configurations for the same generate loop, -incr mode of vopt would incorrectly re-optimize part of the design even when nothing had changed. The re-optimized design may then fail to elaborate correctly. * In a port map, if the actual was an indexed name and the index expression was not globally static the simulator would behave incorrectly. The connection would behave as if the index expression was evaluated once and never re-evaluated. * The compiler could appear to hang when an architecture contained a component instantiation statement that had in its GENERIC or PORT map an actual that contained the name of an object declared in the architecture declarative region, and that object depended on another object in the architecture declarative region, and so on, for several levels of repetition. * The compiler could appear to hang when a package contained a component declaration that had in its GENERIC or PORT clause an default value that contained the name of an object declared in the package, and that object depended on another object in the package, and so on, for several levels of repetition. * The vopt compiler would sometimes issue Errors for indexed names or slice names having out-of-range indexes or bounds when the place was not necessarily reachable (because of being guarded by an IF condition whose value could not be statically determined), or when the place could be determined to be non-reachable because the condition was statically known. * The IEEE.std_logic_1164.RISING_EDGE and S'EVENT and S'LAST_VALUE queries for elements of composite signals would sometimes not return the correct value. * Vopt can run slowly or appear to hang if the constraints on a vector signal are dependent on subtypes declared in the following manner: subtype t0 is std_logic_vector( constant0 downto 0); subtype t1 is std_logic_vector( t0'left+constant0 downto t0'left+1); ... subtype tN is std_logic_vector( tN-1'left+constantN-1 downto tN-1'left+1); Vopt now runs in acceptable times with this. _______________________________________________________________________ FLI Defects Repaired in 10.0c _______________________________________________________________________ VITAL Defects Repaired in 10.0c * The accelerated form of PROCEDURE VitalResolve ( SIGNAL q : OUT std_ulogic; SIGNAL Data : IN std_logic_vector); in vital2000 returned an incorrect value for q. _______________________________________________________________________ SystemC Defects Repaired in 10.0c * SystemC composite type port containing an ac_int type member may sometimes result in a vsim crash during elaboration. This issue has been fixed _______________________________________________________________________ Assertion Defects Repaired in 10.0c * Fixed a bug where assertion control system tasks ($assertoff, $asserton and $assertkill) and assertion action control system tasks ($assertpasson, $assertpassoff, $assertfailon, $assertfailoff, $assertvacuousoff and $assertnonvacuouson) were not working for the parameterized modules and interfaces with multiple specializations. * Fixed a bug where assertion control system tasks ($asserton, $assertoff and $assertkill) were not working for the modules instantiated in generate blocks. * Vsim gave internal error when first_match operator was used over a boolean expression. _______________________________________________________________________ Mixed Language Defects Repaired in 10.0c * If a VHDL signal that crosses mixed language boundaries is driven from Verilog through a hierarchical reference, Verilog signals connected through ports to this VHDL signal will not see the correct values. * When a force of multiple values was done to a Verilog net, that was a subnet of a VHDL signal, a crash could occur. * If a VHDL component had a scalar port but the matching port on a Verilog module was a vector whose width is parameterized, the vopt would generate an error like (vopt-1133) Type mismatch for port MYPORT in component VERILOG_DESIGN when binding to entity VERILOG_DESIGN Vopt no longer generates an error in this case. * A bind statement inside an if generate block with its condition dependent on a floated parameter would always get elaborated in vopt, regardless of what value the if generate block condition evaluates to. The same testcase would work fine in -novopt flow. This has been fixed. * Using SystemVerilog bind construct to bind to a VHDL design-unit would sometimes not bind to all instances of the design-unit in incr flow, if multiple instances of the design-unit were present across certain combinations of SV-VHDL mixed-language boundaries. This has been fixed. * Binding to VHDL target scopes using SV bind construct would make vopt exit with an incorrect error message saying 'expressions are not supported as bind actuals in incremental flow', if option VoptFlow was set to 0 in modelsim.ini. This has been fixed. * Binding to VHDL target scopes using SV bind construct and using an actual of type VHDL unconstrained array of enum, after constraining its dimensions, would result in an incorrect 'illegal use of a VHDL unconstrained array in Verilog' error in vopt. This has been fixed. * VHDL to SV package equivalence had a problem when compiling via "vcom -mixedsvvh" a VHDL package into a given library when that package had a dependence on another package that had been compiled (also with -mixedsvvh) into a different library, and so on, for a dependency depth of 3 or more. The Error vcom-1279 would occur. Note that although the "vcom" problem has been solved, in 10.0, a SystemVerilog design unit that uses such a multiple library-dependent package must still be compiled (with vlog) with the presence of the "-L " options present, one for each library in the set of libraries on which the SV package being used depends. * Compiling a set of VHDL packages into different libraries, when those packages depended on each other, would sometimes cause an error message similar to this: 'Package "c" cannot be imported in SystemVerilog designs.' to occur. This has been fixed. * Correct values would sometimes not be propagated across the SV-VHDL mixed language boundary when VHDL instantiates SV, through bind construct or direct-instantiation, and there is a port connection to an input port with a std_logic type signal as actual and Verilog net as formal. This has been fixed. _______________________________________________________________________ General Defects Repaired in 10.0c * The tools wlf2vcd, wlf2log and dumplog64 did not properly handle VHDL aliases. * (Windows Only) When the Mentor Install Program's "Verify Installation" functionality was used after installation of any ModelSim or Questa product since 6.6, an failure error is reported stating that "...vc2008redist_x86.exe does not exist." This issue has been resolved. * When doing restarts, memory was not being freed and reclaimed. This results in memory a leak which could cause out-of-memory crashes. This issue has been fixed. _______________________________________________________________________ Known Defects in 10.0c * Following FSM design styles are not supported:- 1) Comparing current state variable with a non-constant signal in a condition. 2) Using a relational operator other than equal-to '==' with current state variable in a condition. * Dataflow window will not represent concatenated ports correctly in designs that contain SDF annotation. * The stack unwinder on the linux_x86_64 OS is unreliable. The unwinder is the fundamental facility provided by the OS for sampling where program execution is at. The unwinder is necessary for gathering performance data. This is a known issue with this specific OS and is why performance data will be incorrect or non-existent on this platform. * Specparams can be learned during the learn flow, but cannot be found on consumption. The workaround is to use full +acc deoptimization. * On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal occurs during the simulation and if CDEBUG is on, C-debugger traps the signal, and when continued, vsim gets terminated right away, instead of exiting with proper error status. * The vpiPorts iteration on vpiEnumNet, vpiIntegerNet, and vpiStructNet VPI objects has been disabled as it was incomplete and unsafe to use. * The value annotation in the Schematic window has some known limitations. + MUX output values are not shown in all cases. + Net slices are annotated with the full value of the net, not the value of the slice. Gates that have a slice of a net as input do not show a value on the output. + RTL function output values are not shown in all cases. + Concatenation symbols will not show output values. + Anytime a net is missing a value, downstream gates will also not display any output value. * The Licensing Wizard is not available on the Windows 7 64-bit platform. Use the information in the "Installation and Licensing Guide" to setup your license environment. _______________________________________________________________________ Product Changes to 10.0c * The Verilog compiler now accepts string literals to be enclosed in `" (tick-double-quote) as well as " (double-quotes). Note that the -pedanticerrors switch will disable this extension. * As of Release 10.0, one of the changes to VHDL support is that ModelSim and Questa Sim use certain packages that are now compliant with the current VHDL standard (IEEE Std 1076-2008): ieee.std_logic_1164 ieee.std_logic_textio The characteristics of these packages are not affected by using the -2008 argument to vcom. The ieee.std_logic_1164 package has been made backwards compatible with non-2008 versions, depending on whether you use of the vcom -2008 argument when compiling a design unit that uses the ieee.std_logic_1164 package. However, the std_logic_textio package is not backwards compatible--it will apply the 2008-version of the package, regardless of whether or not you use the -2008 switch to vcom when compiling a design unit that uses ieee.std_logic_textio package. Note that before IEEE Std 1076-2008, the std_logic_textio package was proprietary to Synopsys and was therefore non-standard--it was made compliant with IEEE Std 1076-2008 for Release 10.0. In particular, the current std_logic_textio package causes the HWRITE function to behave a bit differently for producing standard logic values. This is because the new version of std_logic_textio is actually a collection of aliases that point to procedures defined in (2008 version) std_logic_1164. Before 10.0 the HWRITE, accelerated code was following the pre-2008 flow, which used to convert std_logic_vector to bit_vector and then call hwrite(bit_vector). However, as of Release 10.0 (post-2008), there is a separate function in package for std_logic_vector, which handles X and Z values. * As of Release 10.0, one of the changes to VHDL support is that ModelSim and Questa Sim use certain packages that are now compliant with the current VHDL standard (IEEE Std 1076-2008): ieee.std_logic_1164 ieee.std_logic_textio The characteristics of these packages are not affected by using the -2008 argument to vcom. The ieee.std_logic_1164 package has been made backwards compatible with non-2008 versions, depending on whether you use of the vcom -2008 argument when compiling a design unit that uses the ieee.std_logic_1164 package. However, the std_logic_textio package is not backwards compatible--it will apply the 2008-version of the package, regardless of whether or not you use the -2008 switch to vcom when compiling a design unit that uses ieee.std_logic_textio package. Note that before IEEE Std 1076-2008, the std_logic_textio package was proprietary to Synopsys and was therefore non-standard--it was made compliant with IEEE Std 1076-2008 for Release 10.0. In particular, the current std_logic_textio package causes the HWRITE function to behave a bit differently for producing standare logic values. This is because the new version of std_logic_textio is actually a collection of aliases that point to procedures defined in (2008 version) std_logic_1164. Before 10.0 the HWRITE, accelerated code was following the pre-2008 flow, which used to convert std_logic_vector to bit_vector and then call hwrite(bit_vector). However, as of Release 10.0 (post-2008), there is a separate function in package for std_logic_vector, which handles X and Z values. * The implicit package name of the SystemVerilog $unit package is now derived from the name of the first source file given to the vlog command. * DPI use model could be complicated for certain scenarios, for example, - when user libraries of SystemC/FLI/PLI/VPI depend on the DPI export symbols. - when design units with exported DPI functions/tasks are spread into multiple user libraries. - when design units with exported DPI functions/tasks are selectively loaded - when Windows platforms are involved. All of the above scenarios used to require the creation of customized flows based on the "-dpiexportobj" option, which incurs additional overhead in elaboration. The use model of the above scenarios has been simplified. The handling of exports is now automated in a manner transparent to compile and simulate flows. No user intervention is required in the majority of cases (See -dpilib below for an exception). The "-dpiexportobj" option is no longer required and it is now deprecated on Unix/Linux platforms. It is no longer required on Windows platforms if DPI C/C++ source code is compiled using the Questa Sim DPI auto compile feature. The following are two examples along with the illustration of how the use model has been simplified. Example One: SystemC calling DPI-C export function/task // test.sv export "DPI-C" void SVFunction; function void SVFunction; ... endfunction // test.cpp SC_MODULE(sc_top) { void thread() { svSetScope(svGetScopeFromName("top")); SVFunction(); } SC_CTOR(sc_top) { SC_THREAD(thread); } }; Old flow: vlog test.sv sccom test.cpp vsim -dpiexportobj dpiexport top // this generates dpiexport.o sccom -link dpiexport.o vsim -nodpiexports top sc_top -do run.do New flow: vlog test.sv sccom test.cpp sccom -link vsim top sc_top -do run.do Example two: PLI calling DPI-C export function/task // test.sv export "DPI-C" void SVFunction; function void SVFunction; ... endfunction // pli.c int pli_func() { svSetScope(svGetScopeFromName("top")); svFunction(); ... } Old flow: vlog test.sv gcc -shared -o pli.so pli.c vsim -dpiexportobj dpiexport top // this generates dpiexport.o vsim -nodpiexports -gblso dpiexport.so -pli pli.so top -do run.do New flow: vlog test.sv gcc -shared -o pli.so pli.c vsim -pli pli.so top -do run.do Using the "-dpilib" option When the export symbols are spread into multiple libraries, one can use the new "-dpilib" option to specify at the library level the exact export symbols to be loaded. The following is an example of "-dpilib" usage: vlib dpilib1 // create first library vlog work dpilib1 f1.sv // function "int foo (int x)" is being exported from f1. sv vlib dpilib2 // create second library vlog work dpilib2 f2.sv // function "string foo(string x)" is being exported fro m f2.sv vlib dpilib3 // create third library vlog -work dpilib3 f3.sv // function "bar()" is being exported from f3.sv vlib work // work library vlog top.sv // generate top only. In the above example, "foo" is defined in both dpilib1 and dpilib2 with different signatures. To selectively load export symbol "foo" from dpilib1 and export symbol "bar" from dpilib3, one can do: vsim dpilib dpilib1 dpilib dpilib3 top ... If no -dpilib switch is present, vsim will load export symbols from all libraries accessible via vsim options "-L", "-Lf", and "-lib". Please refer to the User Guide for more details and examples. DPI use model could be complicated for certain scenarios, for example, - when user libraries of SystemC/FLI/PLI/VPI depend on the DPI export symbols. - when design units with exported DPI functions/tasks are spread into multiple user libraries. - when design units with exported DPI functions/tasks are selectively loaded - when Windows platforma are involved. All of the above scenarios used to require the creation of customized flows based on the "-dpiexportobj" option, which incurs additional overhead in elaboration. The use model of the above scenarios has been simplified. The handling of exports is now automated in a manner transparent to compile and simulate flows. No user intervention is required in the majority of cases (See -dpilib below for an exception). The "-dpiexportobj" option is no longer required and it is now deprecated on Unix/Linux platforms. It is no longer required on Windows platforms if DPI C/C++ source code is compiled using the Questa Sim DPI auto compile feature. The following are two examples along with the illustration of how the use model has been simplied. Example One: SystemC calling DPI-C export function/task // test.sv export "DPI-C" void SVFunction; function void SVFunction; ... endfunction // test.cpp SC_MODULE(sc_top) { void thread() { svSetScope(svGetScopeFromName("top")); SVFunction(); } SC_CTOR(sc_top) { SC_THREAD(thread); } }; Old flow: vlog test.sv sccom test.cpp vsim -dpiexportobj dpiexport top // this generates dpiexport.o sccom -link dpiexport.o vsim -nodpiexports top sc_top -do run.do New flow: vlog test.sv sccom test.cpp sccom -link vsim top sc_top -do run.do Example two: PLI calling DPI-C export function/task // test.sv export "DPI-C" void SVFunction; function void SVFunction; ... endfunction // pli.c int pli_func() { svSetScope(svGetScopeFromName("top")); svFunction(); ... } Old flow: vlog test.sv gcc -shared -o pli.so pli.c vsim -dpiexportobj dpiexport top // this generates dpiexport.o vsim -nodpiexports -gblso dpiexport.so -pli test.so top -do run.do New flow: vlog test.sv gcc -shared -o pli.so pli.c vsim -pli test.so top -do run.do Using the "-dpilib" option When the export symbols are spread into multiple libraries, one can use the new "-dpilib" option to specify at the library level the exact export symbols to be loaded. The following is an example of "-dpilib" usage: vlib dpilib1 // create first library vlog work dpilib1 f1.sv // function "int foo (int x)" is being exported from f1. sv vlib dpilib2 // create second library vlog work dpilib2 f2.sv // function "string foo(string x)" is being exported fro m f2.sv vlib dpilib3 // create third library vlog -work dpilib3 f3.sv // function "bar()" is being exported from f3.sv vlib work // work library vlog top.sv // generate top only. In the above example, "foo" is defined in both dpilib1 and dpilib2 with different signatures. To selectively load export symbol "foo" from dpilib1 and export symbol "bar" from dpilib3, one can do: vsim dpilib dpilib1 dpilib dpilib3 top ... If no -dpilib switch is present, vsim will load export symbols from all libraries accessible via vsim options "-L", "-Lf", and "-lib". Please refer to the User Guide for more details and examples. The force command now follows a wire model when an input port is forced. This means that the force will be applied at the root of the signal network connected to the input port. The presence of a VHDL conversion function on a connection leading to the port being forced will cause a message to be issued, and for the force command to be ignored. For VHDL designs, when a force command is issued on a VHDL input port, the signal network is traversed up to the root of the network, and the force is applied there. For mixed language designs, the value translations given in the documentation for mixed language port connections are used to provide the value to force when the force is being applied to a network component of a language different than the one specified by the force command itself. When a force command is issued on a Verilog input wire that is connected to a signal network above it, then the network is traversed up to the root of the network, and the force is applied there. If the root is a VHDL signal, then the value is translated according the translations given in the manual for connecting the languages though ports. If VHDL conversion functions are found on path up the network, a message is issued, and the force is not done. An analogous operation is carried out for issuing a force command on a VHDL or System C input port. The vsim command option -nowiremodelforce will cause the old force command semantics to be used. When performing a Drag-n-Drop operation on the Wave or Dataflow windows, "add wave" or "add dataflow" commands will be transcribed respectively for each operation performed. This matches the behavior of the "Add to..." menu selections and toolbar button. When the embedded wave pane within the Dataflow/Schematic window is first shown it will have the visible zoom range set to match that of the last active Wave window if one exists. Also, the wave pane's moveable cursor (Cursor 1) will be moved to the location of the active cursor in the last active Wave window. The Coverage Analysis window has been changed to make it easier to select which analysis type is being viewed and which filter modes are enabled. The buttons that control this selection have been moved so they are directly inside the window. For SystemVerilog DPI support, the use model for locked work libraries is simplified. Exportwrapper generation no longer writes into work library at runtime. No special flow required for locked work libraries environment or distributed simulations environment. Default simulation flow is sufficient. Two existing vsim switches are deprecated as a result: "-dpiexportcheckref" is simply ignored along with a warning. Simulation will continue. "-dpiexportonly" will make vsim immediately return without doing anything. The special "-dpiexportobj" flow is still required ONLY when there is complex dependencies between DPI export and SystemC/PLI/VPI/FLI. This flow is still required on win32 platform. In VRM, repeating runnables now define a built-in parameter whose name is the name of the runnable plus ".ITERATION" and whose value is the current iteration index for that runnable (ie: "testA.ITERATION"). When compiling a Verilog configuration the vlog-19 error, issued when a library is not found, has been replaced by a configuration specific error, vlog-2726. This allows vlog-2726 to be suppressed using -suppress 2726. Suppressing this error may result in design units being loaded from the wrong library. For example, if multiple designs units with the same name are expected to be compiled into multiple libraries, but the library specified in the configuration is missing, a different design unit with the same name may be found depending on the use of -L, -Lf during elaboration. When compiling a verilog configuration the vlog-19 error, issued when a library is not found, has been replaced by a configuration specific error, vlog-2726. This allows vlog-2726 to be suppressed using -suppress 2726. Suppressing this error may result in design units being loaded from the wrong library. For example, if multiple designs units with the same name are expected to be compiled into multiple libraries, but the library specified in the configuration is missing, a different design unit with the same name may be found depending on the use of -L, -Lf during elaboration. Corruption mode option "sc_opt" is now obsolete. It has been removed from Command Syntax vopt error message's. The Objects window filter toolbar has been changed from a 1 of N choice using radio buttons to multiple choice check buttons. Instead of selecting only one of Inputs, Outputs, or Inouts, the check buttons allow for selecting any combination of these three filters plus a fourth option of Internal Signals. The View All button has been retained and a configure button is also added to open the filter configuration dialog box. In the VRM GUI, the time-related columns (simtime, queued, elapsed) now sort in time order rather than lexical order. Syntax errors are now reported slightly differently from the vcom and vlog compilers (the difference is a simple quoting change). For example, this: ** Error: myfile.vhd(6): near "protected": expecting "IDENTIFIER" Is now reported like this: ** Error: myfile.vhd(6): near "protected": expecting IDENTIFIER Presentation and display of VHDL names has changed VHDL is a case insensitive language for all basic identifiers. Prior to 10.0 all VHDL basic identifiers were converted to lower case in vcom. As a results objects like signals, functions, procedure, instance names, variables, and constant, always had their names appear in lower case in messages, the GUI, reports, VCD output, WLF files, and coverage reports. Starting in 10.0 the case of basic identifiers is preserved by vcom. Now object names keep their user given case when being displayed. Pre-10.0 behavior of lowercasing the names can be done by using the -lower switch to vcom or setting the PreserveCase option in the [vcom] section of the modelsim.ini to 0. Design units compiled prior to 6.6 and refreshed to 10.0 will still have object names appear in lowercase. In order to preserve identifier's case, the library database has change slightly. A side effect of this is VHDL design units compiled in 10.0 cannot be refreshed with earlier versions of vcom unless they are compiled with -lower. The supplied precompiled packages in std and ieee have their case preserved. This results in slightly different version numbers for these packages. As a result the user may experience out-of-data reference messages when refreshing to 10.0. To resolve this the user must use -force_refresh. Summary New vcom options -lower Forces VHDL basic identifiers to be stored lower case -preserve Keeps the case of basic identifier. New modelsim.ini options for [vcom] PreserveCase = 1 ; Value of 1 preserve case of basic identifiers ; Value of 0 lower case basic identifiers. Mixed language interactions * Design unit names Because VHDL and Verilog design units are mixed in the same library VHDL design units are treated as if they are lower case. This is for compatibility with previous releases. This also to provide consistent filenames in the file system for make files and scripts. * Verilog packages compiled with -mixedsvvh No change in behavior * VHDL package compiled with -mixedsvvh No change in behavior, VHDL basic identifiers are still lowercased for compatibility with previous releases. * FLI Functions that return names of object will not have the original case unless the source is compiled -lower. Port and Generic names in the mtiInterfaceListT structure are still lower cased to provide compatibility with programs doing case sensitive comparisons (strcmp) on the generic and port names. Call like mti_FindPort, mti_FindSignal, and mti_FindVar, work the same as previous release doing case insensitive look up. The "rebuild libs" functionality for rebuilding the precompiled resource libraries (std, ieee, pa_lib etc.) is no longer supported. The scripts for doing this are no longer provided or supported. The precompiled libraries as delivered are write-protected. The VHDL source for most of the VHDL 2008 IEEE-defined standard packages is no longer available in the installation area because of the copyright that the IEEE has placed on it. The source is available at: http://standards.ieee.org/downloads/1076/1076-2008/ In compliance with the LRM, an input port declaration that does not specify the var keyword now defaults to a net rather than a var. Previously, an input port declaration that included an explicit type defaulted to a var. For example, module xyz(input reg a); The port "a" now defaults to a net, whereas prior to the 10.0 release it defaulted to a var. The var keyword can be used to explicitly declare the port as a var: module xyz(input var reg a); This change is transparent to many designs, but may be problematic for others. The pre-10.0 behavior may be selected by using the vlog compiler option -svinputport=var. Otherwise, if the specified type is not a 4-state scalar or 4-state single dimension vector type, then the rule is relaxed and the input port continues to default to a var: module xyz(input bit a); The type "bit" is not valid for a net, so this port will continue to default to a var. For strict LRM compliance use the vlog compiler option -svinputport=net, and the example above will result in a compile time error. The option -l has been added to vcom, vlog, and vopt to generate a log file of the compilation. The option -version will always report the version of vcom, vlog, and vopt independent of the quiet setting in the modelsim.ini file or if -quiet is specified on the command line. The "coverage analyze ..." viewcov command has been extended to handle bin paths. This enhancement is restricted to non-recursive "-total" style analyze commands. Some vlog error messages have been changed so that they refer to an 'assignment pattern' instead of a 'concatenation'. The use of 'new' with a queue has been supported by Questa, but is not allowed by the LRM. We now print a numbered warning (8491) for this in vlog, vopt, and vsim. This may be suppressed or upgraded to an error. Transaction streams are now only recorded in a WLF file when there are transaction instances on the stream. When reading SystemVerilog, the IEEE 1800-2009 set of keywords is now used by default. Previous versions used the IEEE 1800-2005 set of keywords. Implementing a change in the LRM, we now allow different bits of a packed variable to be driven by continuous and procedural assignments. It is still an error for a given bit to be driven by multiple assignments if one of them is continuous. Verilog hierarchical name resolution has been changed to match the clarified language rules in the P1800-2009 specification. In particular, the rules for upwards name resolution are subtly different. Previously, Questa would attempt to do an upwards lookup on any name in the path that couldn't be found in the target scope so the following Verilog code was accepted in previous releases: module top(); integer top_i=1; generate begin : gen1 integer gen_i=2; end endgenerate initial begin // top_i found in parent of gen1: $display("top.gen1.top_i=%d", top.gen1.top_i); // gen1 matched twice: $display("top.gen1.gen_i=%d", top.gen1.gen1.gen_i); end endmodule In the 10.0 release the names "top.gen1.top_i" and "top.gen1.gen1.gen_i" will fail to resolve. Upwards name lookup still works on the first name in the path so top. will resolve upwards to the module name, but succeeding names will only be resolved downwards. This change impacts various features including vlog/vopt of Verilog source files, SDF annotation, name lookup with FLI and PLI routines, mixed language references between VHDL and Verilog, and lookup of names specified on the command line. We now follow the LRM in initializing an enum to the default value of its base type, rather than the previous method of using the leftmost value. A command-line option that should be used with both vlog and vsim, '-enumfirstinit', will provide the old behavior. One can also set the modelsim.ini variable 'EnumBaseInit' to 0 for the old-style initialization. Conversion of time values to reals has changed. The way to convert a time value to a real is normally done with an expression of the form: real( time_expression_1 / time_expression_2) This conversion is now without truncating the division to 32 bits. In power aware the option '-pa_allowtimezeroevent' has been made default.It will enable power domain(s) to start from corrupted state. If finish_address specified to $readmem is out of bounds, $readmem reads data into the remaining valid memory addresses. Verilog now merges the else-if portions of chains of if-then-else-if-then-else-... statements into a structure resembling VHDL's if-then-elseif-else. This provides a better representation for code coverage. This will not affect the behavior of the design in any way. Verilog now merges the else-if portions of chains of if-then-else-if-then-else-... statements into a structure resembling VHDL's if-then-elsif-else. This provides a better representation for code coverage. This will not affect the behavior of the design in any way. The method that vsim loads dependencies for design-units has changed significantly. Most changes are internal, however the enigmatic property labeled "Package reference number", that appears during the output of "vdir" when the -l option is specified, no longer exists and is not output. In vopt, vcom, and vlog -version will always print the version string even if -quiet is specified on the command line or in the modelsim.ini file. Default visibility of VHDL variables in the vopt flow has been changed. In previous releases, most VHDL variables where still visible after vopt was run. Starting in this release VHDL variables can no longer be examine, changed, or logged unless they are made visible through the use of +acc=v on vopt or -voptargs="+acc=v" on sim. Using +acc=v makes all variable visible in the complete design but can cause slowdowns in simulation performance. It is recommended the +acc=v+ or +acc=v+ be used to make variables visible only in the regions needed. Additionally the switch -vhdlvariablelogging can be used to improve simulation performance when variables are logged. If no variables are logged this option can have a negative impact on simulation. Setting of VhdlVariableLogging to 1 in the modelsim.ini file will make the improved variable logging the default. Therefore VHDL variables are not visible by default in the vopt flow. To log, examine, or change VHDL variables, the variables need to be made accessible through use of +acc=v switch on vopt. It is recommended that you apply the +acc=v option to only the portions of the design where visibility is needed. Please refer to the documentation on how to control object visibility. If the user only wishes to examine or change variables and not log variables, the .ini file setting of VhdlVariableLogging or vsim switches -vhdlvariablelogging and -novhdlvariablelogging. Default visibility of VHDL variables in the vopt flow has been changed. In previous releases, most VHDL variables where still visible after vopt was run. Starting in this release VHDL variables can no longer be examine, changed, or logged unless they are made visible through the use of +acc=v on vopt or -voptargs="+acc=v" on sim. Using +acc=v makes all variable visible in the complete design but can cause slow downs in simulation performance. It is recommended the +acc=v+ or +acc=v+ be used to make variables visible only in the regions needed. Additionally the switch -vhdlvariablelogging can be used to improve simulation performance when variables are logged. If no variables are logged this option can have a negative impact on simulation. Setting of VhdlVariableLogging to 1 in the modelsim.ini file will make the improved variable logging the default. Therefore VHDL variables are not visible by default in the vopt flow. To log, examine, or change VHDL variables, the variables need to be made accessible through use of +acc=v switch on vopt. It is recommended that you apply the +acc=v option to only the portions of the design where visibility is needed. Please refer to the documentation on how to control object visibility. If the user only wishes to examine or change variables and not log variables, the .ini file setting of VhdlVariableLogging or vsim switches -vhdlvariablelogging and -novhdlvariablelogging. On Windows platform, if breakpoint is set on a SystemC object destructor, Debugger sometimes crashes while quitting simulation. This crash can be avoided by setting env variable SC_NO_LIB_UNLOAD, which will prevent unloading of the shared library. The Schematic window has the ability to show signal values annotated on the nets. The default has been changed so the values shown will be for the currently active time, instead of the current simulation time. Some "fsm" switches are folded into a single switch: -fsm=[imrsx] Enable FSM recognition styles * i -- Enable recognition of implicit transitions in FSMs (Off by default) * m -- Enable recognition of Multi-state transitions in FSMs (Off by default) * r -- Enable recognition of implicit asynchronous reset transitions for FSMs (On by Default) * s -- Enable recognition FSMs having single bit current state variables (Off by default) * x -- Enable recognition of FSMs containing X assignments ( on by Default) Any feature above can be toggled by prefixing its literal with "-". For example: "-fsm=-r-xs": * would disable recognition of implicit asynchronous reset transitions * would disable recognition of FSMs containing X assignments * would enable recognition of FSMs having single bit current state variables Searching in the Structure window has changed. In 'Find' mode, search will open a popup list of matches. The user can scroll through the list and select the item of interest. This new search has the following features: * Using a Double-Click on the selected item will cause that item to be selected in the structure window and the popup will be removed. * The search is faster and does not require an 'expand all' beforehand. * Only glob style matches are performed. Glob style includes wildcard (*) and char class ([a-z]) pattern matching. * The search can be canceled by clicking on the close [X] button or by pressing the key. * With 'Search While Typing' enabled (the default) each key press that changes the pattern will restart the search immediately. Known limitation: * this new search does not support regular expression searching or reverse (backwards) searching. * Pattern matching is performed on the leaf name only, not the hierarchical path. * 'Contains' mode searching is not affected by this change and still behaves the same as before with the same limitations. Option -condrow is now -udpcondrow, -cr is now -ucr, -exprrow is now -udpexprrow, -er is now -uer. This change is applicable only to pragma and CLI coverage exclusions. Support of debugging C code during a quit command was disabled on Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. Prior to version 10.0c, Questa and ModelSim included a pre-installed QVL library. In order to ensure that users have the most up to date version of the library it is now available as a separate download. For complete details, please see SupportNet for TechNote #MG552145 titled "Installing Standalone QVL for Questa and ModelSim". Support of debugging C code during a quit command was disabled on Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. _______________________________________________________________________ New Features Added to 10.0c * "Contains" filtering is now supported in the Wave Window. Using the Edit->Find... menu or the ^S shortcut key (^F on Windows), select the "Contains" mode in the search bar if not already selected. * DPI header file will be generated by default from package compilation via "-dpiheader" switch. The package doesn't have to be imported to a design scope first. * The title text in window pane header can be copied using a RMB popup menu. This can be used, for example, to copy the file name of a source file for use elsewhere. * DPI C/C++ library could be compiled automatically with the new DPI auto compile feature. vlog will take C/C++ source files, compile them into object files and store them inside the library. vsim will link these user object files into one single shared library, dpi_auto_compile.so, and load it automatically at the end of elaboration. dpi_auto_compile.so is created on-the-fly in the temp area and will be deleted after vsim exits. New vlog switch: -ccflags <"compileopts">: Specify in quotes all the C/C++ compiler options for vlog/qverilog. Multiple occurrences are supported. New vsim switches: -dpilib <libname>: Specify the design library that contains DPI exports and automatically compiled object files. Multiple occurre nces are supported. -ldflags <"linkopts">: Specify in quotes any options for linking auto compiled DPI object files. Multiple occurrences are supported. New vdel switch: -dpiobj [<platform>|<compiler>|<platform_compiler>|all]: delete all or partially auto compiled DPI object files. 'vdir' can be used to list the existing auto compiled DPI objects in a given library. The following two examples illustrate how to use this feature: Example one: Simple auto compile example with both import and export. // test.sv import "DPI-C" context function void CFunction(); export "DPI-C" void SVFunction; function void SVFunction; ... endfunction // test.c #include "dpiheader.h" void CFunction() { svSetScope(svGetScopeFromName("top")); SVFunction(); } Use flow: 1. vlog -dpiheader dpiheader.h test.sv test.c 2. vsim top -do run.do // no -sv_lib usage required And later if an incremental build is needed after fixing a bug in test.c: 3. vlog test.c 4. vsim top -do run.do // no -sv_lib usage required. Example two: Using "-dpilib" option When the DPI auto compiled object files are spread into multiple libraries, one can use the new "-dpilib" option to specify at the library level the exact object files to be loaded. vlib dpilib1 // create first library vlog work dpilib1 f1.sv f1.c f2.c // f1.o and f2.o are saved in dpilib1 vlib dpilib2 // create second library vlog work dpilib2 g1.sv g1.cpp g2.cpp // g1.o and g2.o are saved in dpilib2 vlib dpilib3 // create third library vlog -work dpilib3 h1.c h2.c h3.cpp // h1.o , h2.o and h3.o are saved in dpilib3 vlib work // work library vlog top.sv // generate top only. In the above example, three libraries with DPI auto compiled objects are created. To selectively load the object files from dpilib1 and dpilib2, one can do: vsim dpilib dpilib1 dpilib dpilib2 top ... If no -dpilib switch is present, vsim will load export symbols from all libraries accessible via vsim options "-L", "-Lf", and "-lib". Refer to the User Guide for more details and examples. * DPI C/C++ library could be compiled automatically with the new DPI auto compile feature. vlog will take C/C++ source files, compile them into object files and store them inside the library. vsim will link these user object files into one single shared library, dpi_auto_compile.so, and load it automatically at the end of elaboration. dpi_auto_compile.so is created on-the-fly in the temp area and will be deleted after vsim exits. New vlog switch: -ccflags <"compileopts">: Specify in quotes all the C/C++ compiler options for vlog/qverilog. Multiple occurences are supported. New vsim switches: -dpilib <libname>: Specify the design library that contains DPI exports and automatically compiled object files. Multiple occuren ces are supported. -ldflags <"linkopts">: Specify in quotes any options for linking auto compiled DPI object files. Multiple occurences are supported. New vdel switch: -dpiobj [<platform>|<compiler>|<platform_compiler>|all]: delete all or partially auto compiled DPI object files. 'vdir' can be used to list the existing auto compiled DPI objects in a given library. The following two examples illustrate how to use this feature: Example one: Simple auto compile example with both import and export. // test.sv import "DPI-C" context function void CFunction(); export "DPI-C" void SVFunction; function void SVFunction; ... endfunction // test.c #include "dpiheader.h" void CFunction() { svSetScope(svGetScopeFromName("top")); SVFunction(); } Use flow: 1. vlog -dpiheader dpiheader.h test.sv test.c 2. vsim top -do run.do // no -sv_lib usage required And later if an incremental build is needed after fixing a bug in test.c: 3. vlog test.c 4. vsim top -do run.do // no -sv_lib usage required. Example two: Using "-dpilib" option When the DPI auto compiled object files are spread into multiple libraries, one can use the new "-dpilib" option to specify at the library level the exact object files to be loaded. vlib dpilib1 // create first library vlog work dpilib1 f1.sv f1.c f2.c // f1.o and f2.o are saved in dpilib1 vlib dpilib2 // create second library vlog work dpilib2 g1.sv g1.cpp g2.cpp // g1.o and g2.o are saved in dpilib2 vlib dpilib3 // create third library vlog -work dpilib3 h1.c h2.c h3.cpp // h1.o , h2.o and h3.o are saved in dpilib3 vlib work // work library vlog top.sv // generate top only. In the above example, three libraries with DPI auto compiled objects are created. To selectively load the object files from dpilib1 and dpilib2, one can do: vsim dpilib dpilib1 dpilib dpilib2 top ... If no -dpilib switch is present, vsim will load export symbols from all libraries accessible via vsim options "-L", "-Lf", and "-lib". Refer to the User Guide for more details and examples. * In VRM, the "src" attribute of "localfile" elements in the RMDB now supports wildcard globbing (according to the rules for the TCL 'glob' command). Globbing works under the following conditions: + If the "name" attribute is blank or does not exist, the files referred to by the "src" attribute will be copied/linked into the working directory for the Runnable on whose behalf the "localfile" element is being expanded. + If the "name" attribute is non-blank and refers to a directory, the files referred to by the "src" attribute will be copied/linked into the directory referred to by the "name" attribute. If the "src" attribute expands to more than one source file and the "name" attribute is non-blank and does not refer to a directory, an error will be reported and the "localfile" element will not copy/link any files.