| Table 1. Demonstration Topics |
| Quartus II Topic |
Online Demonstration Modules |
| Quartus II Software Overview |
- Compile Your First Design Using Quartus II Software
- Introductory Information About Quartus II Software
|
| Basic FPGA/CPLD Design |
- Design Entry
- Compilation
- TimeQuest Timing Analyzer
- Simulation
- Programming
- Scripting
|
| Design Flows |
- MAX+PLUS® II Project Conversion to the Quartus II Software
- MAX+PLUS II User Interface
- System Design Using SOPC Builder
- Importing Custom Peripherals into SOPC Builder
- Creating Multi-Clock Domain Systems
- Designing for HardCopy® II Structured ASIC Devices
- Nios® II Processor C-to-Hardware Acceleration Compiler
|
| Design Optimization and Implementation |
- Integrated Cross Probing
- Optimization Advisors Provide Design-Specific Suggestions to Improve Design Results
- Using the RTL Viewer and Technology Map Viewer to Check Synthesis and Fitting Results
- Using I/O Assignment Analysis to Validate Pin Assignments Early
- Timing Closure Floorplan
- Netlist Optimization Improves Push-Button Results
- Design Space Explorer to Increase Design Performance
|
| Reducing Design Cycles |
- Incremental Compilation and Team-Based Design
- Integrated Cross Probing
- Using I/O Assignment Analysis to Validate Pin Assignments Early
|
| Verification |
- TimeQuest Timing Analyzer
- Analyzing and Optimizing Power in FPGAs
- Update FPGA Memory Contents In-System to Facilitate Verification
- Perform a Functional and/or a Timing Simulation with the Model TechnologyTM ModelSim®-Altera Software
|
Literature
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