Asia Pacific Technology Roadshow 2008
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Date: July 2008
Region: Asia Pacific
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Altera Technology Roadshow will be held in China, India, Korea, Malaysia, Singapore, and Taiwan. You can get the complete event agenda, presentation abstract and registration contacts below.
Agenda
Notes:
- Agenda varies with cites
- Click on the presentation title for a brief description of the session
Event Schedule and Registration Contacts
China
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Date
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City
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Registration Contacts
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July 3, 2008
1:00 pm - 5:30 pm
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Shanghai
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Wintech: Jojo Zhu
Email: jojo.zhu@wtmec.com
Tel: 86-21-5875 0858 ext. 5701
Fax: 86-21-5875 6690
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July 8, 2008
1:00 pm - 5:30 pm
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Nanjing
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Achieva: Maggie Liang
Email: maggie.liang@achievaglobal.com
Tel: 86- 21-5308 0560 ext. 600, 139-1724 5482
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July 15, 2008
1:00 pm - 5:30 pm
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Xi'an
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Arrow: David Xue
Email: david.xue@arrowasia.com
Tel: 86-28-8620 3226 ext. 213 or 133-0822 7596
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July 17, 2008
1:00 pm - 5:30 pm
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Beijing
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Future: Karin Feng
Email: karin.feng@futureelectronics.com
Tel: 86-10-64182335 ext.211
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July 29, 2008
1:00 pm - 5:30 pm
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Chengdu
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Cytech: Sandy Sun
Email: sandysun@cytech.com
Tel: 86-28-8652 7116
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India
Please download and fax the completed registration form to our distributor in India.
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Date
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City
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Registration Contacts
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July 8, 2008
9:00 am - 3:30 pm
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Hyderabad
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Achieva India : Malhar Deshpande
Email: malhar.deshpande@achievaglobal.com
Tel: 91-80-2520 2348 ext. 301
Fax: 91-80-2520 1868
Wintech India: Sateesh Babu
Email: sateesh.babu@wtmec.com
Tel: 91-80-2678 1048/ 91-98-8608 5390
Altera India: Nandini Sunderraj
Email: nsunderraj@altera.com
Tel: 91-80-6616 1755
Fax: 91-80-6616 1751
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July 10, 2008
9:00 am - 3:30 pm
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Pune
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Korea
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Date
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City
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Registration Contacts
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July 2, 2008
9:30 am - 3:30 pm
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Seoul
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Uniquest Korea: Ellis Kwon
Email: ellis@infinitek.co.kr
Tel: 82-31-776 9932
Wintech Microelectronics Korea: Teresa Park
Email: teresa.park@wtmec.com
Tel: 82-31-385 5775
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Malaysia
Please download and fax the completed registration form to our distributor in Malaysia.
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Date
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City
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Registration Contacts
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July 24, 2008
9:00 am - 3:30 pm
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Penang
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Achieva Singapore: Ng Lee Koon
Email: lkng@achieva.com.sg
Tel: 65-6840 3117
Fax: 65-6747 6880
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Singapore
Please download and fax the completed registration form to our distributor in Singapore.
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Date
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City
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Registration Contacts
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July 23, 2008
9:00 am - 3:30 pm
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Singapore
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Achieva Singapore: Ng Lee Koon
Email: lkng@achieva.com.sg
Tel: 65-6840 3117
Fax: 65-6747 6880
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Taiwan
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Date
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City
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Registration Contacts
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July 15, 2008
1:00 am - 5:30 pm
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Taipei
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Galaxy Taiwan: Chili Kung
Email: chil ik721@gfec.com.tw
Tel: 886-2-8913 2200 ext.209
Wintech Taiwan: Michelle Huang
Email: michelle.huang@wtmec.com
Tel: 886-2-8226 9088 ext. 8509
Altera Taiwan: Evina Lin
Email: evlin@altera.com
Tel: 886-2-2514 8068 ext. 199
Fax: 886-2-2545 5952
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July 17, 2008
1:00 am - 5:30 pm
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Hsinchu
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Presentation Abstract
Benefits and Challenges of 40-nm Process Technology
Semiconductor vendors have aggressively migrated to smaller process geometries with the expectation of reducing cost, increasing performance, and adding an enhanced feature set to their products. Altera recently introduced the FPGA industry's first 40-nm custom logic devices—Stratix® IV FPGAs and HardCopy® IV ASICs. This presentation explores the benefits one can expect from TSMC's latest process technology, Altera's transceiver innovation, and robust IC design for manufacturing methodology.
Designing with Transceiver-Based FPGAs at 40 nm
High-speed transceivers are finding their way into many applications such as networking, telecommunication, broadcast, military, wireless, industrial, and storage. Transceivers were once considered as niche products meant only for bandwidth-critical applications such as internet backbone infrastructure. Trends suggest that transceivers will become very common across the different applications mentioned above due to market dynamics evolving towards broader adoption of high-speed serial protocols. This presentation will cover some of the technology aspects of implementing high-speed serial protocols such as PCI Express, CEI-6G, serial digital interface (SDI), Gigabit Ethernet, Serial RapidIO® (SRIO) standard, XAUI, SerialLite II, Fibre Channel, and SONET standards. This presentation will also cover details on how FPGA vendors are incorporating these high-speed serial protocols.
Why You'll Want to Think Altera When You Think About Your Next Embedded System
Few electronic systems are much more convoluted than embedded systems, in which performance (required by graphic acceleration), power consumption, price, flexibility, and time-to-market all need to be taken into account. When such challenges arise, think Altera® embedded technology. Altera embedded technology solutions, based on Altera devices and software, make it much easier to meet the requirements of customization, flexibility, time-to-market, and cost-effectiveness. In this technical session, you will learn why so many developers choose Altera embedded technology, watch a real demo example, and learn how to turn your system concept into reality quickly and cost-effectively.
How to Facilitate Advanced DSP Design When Facing Performance and Time-to-Market Challenges
The advanced digital signal processing (DSP) designer's challenge of meeting increasing demand for DSP performance when time-to-market for the project is decreasing can be now tackled by FPGA-based DSP solutions. Parallel hardware processing and advanced modeling technology are derived from the powerful performance and short time-to-market characteristics of the FPGA-based DSP system. In this technical session, you will learn about current DSP trends; the DSP capability of Altera's new 40-nm FPGAs; IP that facilitates DSP design; FPGA-based DSP design flow using The MathWorks MATLAB, Simulink, and Altera's DSP Builder; and a typical repeater application example.
Altera's Innovative Custom Logic Solutions for the Industrial Market
Altera programmable logic devices (PLDs) are being integrated into a growing array of industrial designs. From programmable logic controllers (PLCs) and I/O modules to servo drives and motion controllers, products based on PLDs can be quickly modified to support new functionalities or requirements. Since PLD designs are based on intellectual property and HDL, they can be migrated easily to different devices or even to new generations of PLDs. This flexibility, along with the longevity of PLDs, means you don't have to worry about obsolescence. In this presentation, we will introduce you to Altera's innovative solutions for the industrial market, including industrial Ethernet, HMI, and motion controllers. You will learn how to use Altera and Altera partners FPGA-based solutions to implement various industrial systems.
Altera's Innovative Custom Logic Solutions for Advanced Military Applications
FPGAs have always been used in military applications due to their inherent advantages of flexibility and scalability. You can use FPGAs in different areas of military systems such as secure communications, radar and sensors, electronic warfare, software defined radio (SDR), commercial off-the-shelf (COTS) computers, and guidance and control. Altera's newer generation of FPGAs bring in several new features geared specifically towards the military market such as design security; International Traffic in Arms Regulation (ITAR) compliance; size, weight, and power (SWaP) requirements; embedded processors, and complete system implementation capability. This presentation highlights the value proposition of implementing advanced military applications using Altera FPGAs.
Altera's innovative IP Solutions Overview
Altera offers a broad portfolio of easy-to-use IP cores. These IP cores are high quality “building blocks” that you can drop into your system designs, avoiding the time consuming task of creating complete design from scratch. Easy-to-use, pre-verified, and configurable, Altera IP is optimized for the latest Altera devices and fully supported in Quartus® II design software. Some of the IP cores are offered by leading third-party IP vendors who have developed and optimized for Altera devices. In this presentation, you will discover how quickly you can use these IP cores to accelerate your system design, lower development cost, and speed your time-to-market.
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Literature
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