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October 14, 2008 - Bangalore, India |
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| Time | Topic | ||
| 8:30 to 9:20 | Registration | ||
| 9:20 to 11:05 | Exhibition | Opening and Welcome Speech | |
| First Lucky Draw | |||
| Multi-Processing for Higher Performance and Lower Power | |||
| Guest Speaker | |||
| 11:05 to 11:20 | Tea Break | ||
| 11:20 to 11:50 | Power Down, Speed Up with Altera Products | ||
| 11:50 to 1:15 | Second Lucky Draw and Lunch Break | ||
| Time | Track 1: High Performance |
Track 2: Low Cost
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| 1:15 to 2:00 | Exhibition | ||
| 2:00 to 2:15 | Break | ||
| 2:15 to 2:55 | Leading Edge Verification Techniques Using Aldec Active-HDL Mixed Language Simulation for Altera® FPGA Designs. |
Quickly Create Your Portable Designs by Using Altera CPLDs |
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| 2:55 to 3:10 | Break | ||
| 3:10 to 3:50 | |||
| 3:50 to 4:15 |
3rd Lucky Draw and Closing
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Morning Session
Multi-Processing for Higher Performance and Lower Power
In this new era of climate change, next generation electronic applications will require more efficient power management than ever while still reaching performance levels which continue to rise. To meet these dual market demands, the industry must look to flexible technology that better economizes power and boosts performance at the same time. Because of their unique capabilities, FPGAs are the ideal solution for keeping performance up while dramatically dropping power consumption over equivalent ASSP and ASIC functions. Come see how advancements to FPGAs and FPGA design tools now allow you to use hardware acceleration to offer unparalleled performance with the lowest possible power footprint.
Power Down, Speed Up with Altera Products
Earlier this decade, Altera realized power was fast becoming the most important factor for all semiconductor designs. From handheld to large infrastructure applications and everything in between, power affects cost, performance, reliability, and longevity of all end products. To address this challenge, Altera began a long term effort to reduce power in its portfolio of CPLDs, FPGAs, and ASICs by focusing on process advancements, new innovative power management technology and power optimized design tools. All of this was done in conjunction with innovations to increase device performance. The result is a complete portfolio of devices that allow you to power down AND speed up.
Afternoon Session
Track 1
Reach New Levels of SoC Integration with 40-nm FPGAs
FPGAs are an ideal platform for system-on-a-chip (SoC) integration due to their inherent flexibility and time-to-market advantages. Altera's 40-nm custom logic portfolio, which includes the new Stratix® IV FPGAs and HardCopy® IV ASICs, offers benefits in terms of density, performance, features, and interface bandwidth for new levels of SoC integration.
Leading Edge Verification Techniques Using Aldec Active-HDL Mixed Language Simulation for Altera FPGA Designs
By Aldec
This seminar demonstrates the latest Aldec verification techniques that will take you to the next level when verifying complex designs targeted to Altera's high-performance/capacity FPGAs. The seminar shows leading edge verification techniques such as assertion-based verification, functional coverage, simulation optimization and advanced debugging techniques which can help in achieving more accurate and comprehensive verification of Altera® FPGAs.
Model-Based Design for Communication Systems with The MathWorks' Simulink and Altera's DSP Builder;
a WiMAX Design Example
By The MathWorks
Model-Based Design is a methodology for designing embedded hardware and software systems. It provides platform-to-perform high-level design exploration and optimizations, and a formal model to support and verify the application at design time. This tutorial explores how Simulink from The MathWorks, together with Altera DSP Builder, dramatically shortens design time and produces optimized implementations in Altera FPGAs.
The presentation will demonstrate an end-to-end baseband model of the physical layer of the WiMAX IEEE 802.16-2004 standard. Specifically, it will model the OFDM-based physical layer supporting all of the mandatory coding and modulation options. It will also illustrate space-time block coding (STBC), an optional transmit diversity scheme specified for use on the downlink. Then, we will discuss FPGA implementation techniques using Altera DSP Builder.
Track 2
Increase Performance and Reduce Power Using Altera's Embedded Solutions Portfolio
Embedded processing designers today are faced with the dilemma of meeting demand for increased performance, driven by end applications, and also the call for decreased power, spurred by energy concerns. The balance of performance and power has always been a tradeoff, in which design, system architecture, component-level performance and power, are all taken into account . . . until now. During this technical session's presentation and live demonstration, you will learn how Altera's comprehensive portfolio of embedded solutions, devices, intellectual property, design software, reference designs, and development kits with real examples enables your designs to have both increased performance AND reduced power.
Quickly Create Your Portable Designs by Using Altera CPLDs
CPLDs provide advantages needed for success in the world of portable application design—they are a fast, inexpensive, low-risk way to quickly customize off-the-shelf chipsets. In addition, CPLDs are ideal for voltage level shifting in a mixed voltage environment, for general-purpose I/O pin expansion, and for bridging between different interface protocols.
In this presentation, you'll see how designers of portable applications are using CPLDs to quickly create highly competitive, cutting-edge products, and learn how you can use Altera CPLDs to accelerate your next portable application design process.
Creating Low-Cost Control Networks with Altera FPGAs
By Echelon
The LonWorks platform from Echelon Corporation, combined with Altera's Nios® II embedded CPU core and Cyclone® II and Cyclone III FPGAs, enables a new generation of green and energy aware products for consumer, commercial and industrial applications. Echelon provides free interface software to Altera customers developing applications for consumer appliances using Power Line Smart Transceivers and complex system controllers, and area controllers using free Topology Smart Transceivers. Developers have the freedom to select the best combination of soft-core processor and peripherals for their application.
Please contact your distributor in India for more details on SOPC World 2008 India.
Altera India: Nandini Sunderraj
Email: nsunderr@altera.com
Phone: 91-80-6616 1755
Fax: 91-80-6616 1751
Arrow India: Malhar Deshpande
Email: malhar.deshpande@achievaglobal.com
Phone: 91-80-4135 3754
Wintech India: Sateesh Babu
Email: sateesh.babu@wtmec.com
Phone: 91-80-2678 1048/ 91-98-8608 5390
If you would like someone to contact you regarding Altera's high-speed SOPC solutions, please email SOPCWorldAsia@altera.com.
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