Code:DSP Seminars
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Dates & Locations
- 27 June 2005—
Munich, Germany
- 29 June 2005—
Paris, France
- 30 June 2005—
Oxford, UK
|
Code:DSP Video, Image & Signal Processing Seminars
Altera's Code:DSP video, image and signal processing solutions allow designers to implement the next-generation of FPGA-based system architectures that boost digital signal processing (DSP) performance and lower overall costs. This is a full-day seminar that brings together top global companies and leading-edge products so you can learn about:
- Lowering Costs Using Cyclone® II FPGAs & HardCopy® II ASICs
- Architecting Systems With DSP Processors & FPGA Co-Processors
- Design Flows Including MATLAB/Simulink & ‘C’ Language EDA Tools
- Compression Solutions: JPEG2000, MPEG4, H.264 & Windows Media 9
- Video I/O Implementations Including ASI, HD/SD-SDI & Video-Over-IP
Altera will be supported by a host of partners and industry experts, delivering emerging technology demonstrations and presentations designed to update and educate engineers, system architects, and project managers on video and image processing solutions. These will include:
Altera's Code:DSP Video, Image and Signal Processing seminars are also supported by partners
from the board, IP, and design tool industries.
| Event Agenda |
| Time |
Activity |
Key Topics Covered |
Presenter(s) |
| 09:00 |
Breakfast/Registration |
| 09:30 |
Video, Image and Signal Processing With FPGAs |
- Reducing system cost with 90-nm FPGAs and HardCopy ASICs
- System design flow considerations and solutions
|
Altera
|
| 10:10 |
Model-Based Design Tutorial With Simulink |
- Create a model-based design in Simulink and optimize system level specifications
- Integrate the data path and control processing
- Generate FPGA design and verify real-time video application in hardware
|
The MathWorks
Altera |
| 11:15 |
Break |
| 11:30 |
Panel Discussion: Developing FPGA Co-Processors Using ‘C’ Language & Modeling Tools |
- The panel will address key questions surrounding modeling and ‘C’ language EDA tools for FPGAs, including industry adoption, quality of results, system integration issues, and technology roadmaps, plus audience questions
|
Celoxica
Mentor Graphics
Synplicity
The Mathworks |
| 12:30 |
Lunch (Exhibit Area Open) |
| 14:30 |
DSP and FPGA: The Ideal Complementary Choice to Achieve High-Performance and Flexibility in Video Processing |
- Partitioning a design between FPGA co-processors and DSP processors
- FPGA/DSP development tools and board support package
- Co-processor demonstration using an Ateme video and imaging development platform
|
Texas Instruments |
| 15:45 |
Break |
| 16:00 |
Low-Cost Solutions for Video Compression Systems |
- Designing FPGA-based systems with JPEG2000/MPEG4 compression and pre/post processing techniques including video conversion, scaling, and noise reduction
- Explore what can be implemented in low-cost FPGAs and HardCopy ASICs at different price targets
|
Barco |
| 17:15 |
Close |
| Schedule |
| Date |
City |
Location |
| 27 June 05 |
Munich, Germany |
Arabella Sheraton Bogenhausen Hotel
ArabellaStrasse 5
Munich 81925
GERMANY
Tel: 00 49 89 92 320
www.starwoodhotels.com |
| 29 June 05 |
Paris, France |
Sofitel Paris Porte de Sevres
8-12, rue Louis Armand
75015 Paris
FRANCE
Tel : 00 331 40 60 30 30
www.sofitel.com |
| 30 June 05 |
Oxford, UK |
WilliamsF1 Conference Centre
Grove
Wantage
Oxfordshire OX12 0DQ
UK
Tel: 00 44 (0)1235 777 900
www.williamsf1conferences.com |
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