Attend Altera’s free, practical workshop to learn about the important silicon, board, and system solutions you can use to achieve optimal signal integrity in your high-speed serial applications.
Other sessions will focus on high-speed channel design, power distribution network design, and transceiver architecture. There will be product demonstrations of PCI Express (PCIe) and 10-Gbps transceiver operation.
These workshops will give you all the knowledge and tools to make your next high-speed design easy.
Where:
Hotel Antonella, Via Pontina Km 28
00040, Pomezia
Rome, Italy
When:
24th September, 2009
Featured Technology
Stratix® IV GX, Stratix IV GT, and Arria® II GX FPGAs, and HardCopy® IV GX ASICs
Participating Partners
Specialists from these participating partners will guide you through the latest solutions for meeting transceiver design challenges:
- Mentor Graphics®
- Tektronix
- Linear Technology
Agenda
| Time | Session |
| 09:00 - 09:15 | Registration |
| 09:15 - 09:30 | Introduction and Product Portfolio |
| 09:30 - 10:15 | Transceiver Architecture, Jitter, Eye Diagram, BER - Part 1 |
| 10:15 - 10:30 | Break |
| 10:30 - 12:30 | Transceiver Architecture, Jitter, Eye Diagram, BER - Part 2 & Signal Integrity Lab |
| 12:30 - 13:15 |
Lunch + 10-Gbps Demo |
| 13:15 - 14:30 | Power Supply Solutions and Power Distribution Network – Lecture and Lab |
| 14:30 - 14:45 | Break |
| 14:45 - 15:30 | PCI Express Lecture and Demonstration |
| 15:30 - 16:30 | Transceiver Board Design Guidelines and Simulation |
| Closing Remarks |
Additional Information
Learn more about Altera’s 40-nm devices with transceivers:
- Stratix IV GX and GT FPGAs: High-density, low-power devices with up to 11.3-Gbps transceivers
- Arria II GX FPGAs: Low-cost transceiver FPGAs with high-end capabilities (transceiver speeds up to 3.75 Gbps)
- HardCopy IV GX ASICs: Low risk, low total cost, and fast-time-to-market solutions with 6.5+ Gbps transceivers
Visit the Altera® Board Design Resource Center, a comprehensive repository of signal integrity and board design guidelines, and information.
