Free hands on Video Processing Workshop
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Dates and Locations |
Join us for a free hands-on video processing workshop and boost your design productivity with FPGA
The workshop will walk you through the end-to-end construction of a scalable, multi-channel, high bit-rate video system, including practical designs to be built and tested on Altera® A/V FPGA development platforms.
Agenda:
- Introduction
- Labs 1, 2, and 3 will involve practical design and testing with all attendees (teamwork)
- Lab1: Using SOPC Builder for Video Output
- Get acquainted with the Quartus II top-level HDL template
- Get familiar with the SOPC Builder flow to build systems with the Video IP framework
- Use the video framework to achieve a progressive test pattern (1280x720) output via SDI
- Lab2: Nios II and Video Input
- Build a design with a Nios II soft processor
- Observe the Avalon®-ST video protocol in action in a system that enables run-time change of output video resolution
- Get familiar with the Clocked Video Input (CVI) IP function
- Lab3: Frame Sync
- Design a video datapath that requires an external memory
- External DDR Memory controller, Clock domains
- Understand how memory bandwidth can be optimized
- Bank interleaving, on-chip buffering, pipeline bridges, burst sizes
- Boot Nios II soft processor from Flash to run in DDR
The course supervisor will provide a detailed walk-through of Labs 4 and 5 to familiarize the delegates with Quartus/SOPC project, architecture, IP configuration and testing.
- Lab4: Video Processing
- Design a full, configurable video datapath from input to output
- Add video processing functions to perform appropriate format conversions
- Clippers, scaler, chroma resamplers, deinterlacer, switch and mixer
- Lab5: Add a second video processing chain
- Memory bandwidth calculations
- Include the Altera Multi-Port Front End interface to memory
- Two independent channels, Picture In Picture
- Partner presentation Omnitek
- Streaming video over PCIe – Presentation and demonstration
- The Altera Video Processing roadmap and expert discussion
Prerequisites
We recommend delegates complete the following courses:
- Implementing Video Systems (ODSP1118)
- This is a free online course (1.5 Hours) which introduces Altera’s video platform and design flow
- Designing with the Nios II processor and SOPC Builder (OEMB1116)
- This is a free online course (8 Hours)
We recommend you view the following webcast:
- Remove the External Memory Bottleneck in Your Video Design
- Learn about highly efficient memory access for high-quality video applications (25 Mins).
Registration
Attendance is free. However, as we expect delegates to complete the above preparation, pre-qualification may be required to ensure attendees are able to complete the labs on this busy day.
Please register your interest by emailing Audrey Burson: we will email a confirmation in return.
All lab content (reference designs, presentation materials, and documentation) will be made available to attendees.
