40th Design Automation Conference (DAC)
Overview
The Design Automation Conference (DAC) is an annual event that highlights design methodology for EDA and silicon solutions. DAC features more than 50 technical sessions covering the latest in design methodologies and EDA tool development and an exhibition and demo suite area with over 250 of the leading EDA, silicon, and intellectual property (IP) providers.
Panel Discussion – Wednesday, June 4
Altera will participate in a panel discussion on the best methods of obtaining and implementing IP cores on Wednesday, June 4, 2003, 12:00 to 2:00 PM.
Craig Lytle, Vice President of Altera's Intellectual Property Business Unit, will participate in this luncheon panel presented by VSI Alliance. Ron Wilson of EE Times will moderate the discussion about how intellectual property cores should be obtained and used. Representatives from LSI Logic, Phillips Semiconductors, TSMC, and Tensilica will also participate.
Altera Featured Technology
Altera is pleased to be working with our many EDA ACCESS Program® partners at this year's DAC to demonstrate how easy it is to design Altera® system-on-a-programmable-chip (SOPC) solutions using industry-leading third-party EDA tools including those from Mentor and Synplicity.
Altera will be showcasing the Nios® development kits and Altera EDA partners will use both the Nios Development Kit, Stratix™ Edition and the Nios Development Kit, Cyclone™ Edition in software demos. These Nios development kits include the Quartus® II design software and SOPC Builder, an automated system development tool used to develop Nios processor-based systems.
The Quartus II software is the most comprehensive environment available for SOPC design. It includes the LogicLock™ block-based design flow, making it the only programmable logic device software with incremental design as a standard feature. This feature increases designer productivity and shortens design and verification cycles.
SOPC Builder is a development tool that dramatically simplifies creating high-performance SOPC designs. It accelerates time-to-market by automating the system definition, integration, and verification phases of SOPC development. Using SOPC Builder, system designers can define a complete system from hardware to software—all within one tool and in a fraction of the time of traditional system on a chip (SOC) design.
Altera's SOPC solutions can be designed with tools offered by Altera EDA partners. Please visit Altera EDA partners' booths (listed in Table 1).
Conference & Expo Site Information
Anaheim Convention Center
800 West Katella Ave.
Anaheim, CA 92802
Anaheim Convention Center web site
Related Links
If you would like someone to contact you regarding Altera's high-speed SOPC solutions, please e-mail workshop@altera.com.
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