Enabling Tomorrow's Products Today—Visit Altera at DesignCon 2008

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Dates: February 4-7, 2008 Featured Technology:  Stratix®  III, Stratix II GX,  Stratix II , 10-Gbit Test Chip Location: Santa Clara Convention Center Region: North America Events Event URL: http://www.designcon.com/2008/

Learn how FPGA architectural innovations and technologies enable high I/O performance, best-in-class signal integrity, and low power consumption. Altera^® Stratix series FPGAs enable you to create a rock-solid foundation for the most demanding applications.

Innovate, differentiate, and win with Altera—See technology demos at Altera’s exhibitor booth 429

Stratix III—The only FPGA architecture with Programmable Power Technology

• Stratix III FPGAs deliver up to 50% lower power with 35% higher performance and 2X higher density compared to previous-generation devices
• Quartus^® II development software automatically selects lowest power logic while delivering system performance requirements and timing closure

Stratix III—The only FPGA architecture with 1067-Mbps DDR3 memory interface support

• Delivers high-performance DDR3 1067-Mbps interface with margin
• Provides JEDEC-compliant DDR3 DIMM capability through read/write leveling
• Supplies power savings from dynamic on-chip termination (OCT) and the low supply voltage of DDR3 memory

Stratix II GX—The only FPGA architecture with dynamic reconfiguration

• Deliver flexibility and reduce system cost by enabling customers to reconfigure serial channels in the field with minimal downtime
• Dynamically change transceivers data rates, protocols and PMA settings without interrupting other channels
• Dynamically optimize signal integrity for 6.375-Gbps backplane applications

Stratix II GX—The only FPGA architecture with Plug & Play Signal Integrity

• Automatically reconfigures backplane equalization settings
• Automatically maintains optimal signal integrity at high data rates
• Enables you to design truly universal cards that plug into multiple card positions

10-Gbit Test Chip—The most advanced FPGA transceiver technology showing 10-Gbit operation

• Demonstrates the robust performance margins and optimal signal integrity in Altera’s transceiver technologies

Review Conference Technical Papers Presented by Altera

Time	Technical Papers Presented by Altera
Tuesday, February 5
8:30am – 9:10am	8-TA1 Analysis of Crosstalk Effects on Jitter in Transceivers
10:15am – 10:55am	13-TA3 Study of Fundamental Limit and Packaging Technology Solutions for 40-Gbps Transceiver Package Design 1-TA4 A Reset Control Apparatus for Phase-Locked Loop (PLL) Power-Up Sequence and Auto-Synchronization
Wednesday, February 6
8:45am – 9:25am	3-WA1 Using Programmable Logic for Receiver Offset and Yield Enhancement 6-WA1 A Fast Algorithm to Instantly Predict FPGA Simultaneous Switching Noise (SSN) for Various I/O Pin Assignments 12-WA1 A Jitter Estimation Method for Cascaded, Programmable PLLs
9:40am – 10:20am	6-WA2 Challenges in Implementing DDR3 Memory Interface on PCB Systems: a Methodology for Interfacing DDR3 SDRAM DIMM to an FPGA
2:00pm – 2:40pm	4-WP1 Process and Temperature Variations on Electrical Parameters of Wire-Bond BGA Packages: an Impact Analysis Using Simulation-Based DOE Methodology
2:50pm – 3:30pm	4-WP2 FPGA I/O Timing Variations Due to Simultaneous Switching Outputs (SSOs) 14-WP2 Modeling FPGA Current Waveform and Spectrum and PDN Noise Estimation

Keynote Address

Tuesday, February 5
Noon- 12:30pm

Dr. Misha Burich
Senior vice president, R&D, Altera Corporation

Title:  "Programmable Solutions: A Continued Evolution"

Now, more than ever before, there is a pressure in the electronics industry to shorten time-to-market, to lower development costs, and offer product variations and options. To satisfy these requirements, the semiconductor industry continues to innovate in providing programmable solutions that can be rapidly adapted and deployed by their customers to their end users.

Misha Burich, Altera’s senior vice president of research and development, will describe current and future promising technologies that satisfy these requirements, including the spectrum from fine-grained to coarse-grained multi-cores and rapidly customizable ASSP solutions.

Tech Forum

Monday, February 4
1:30pm – 4:30pm

Dr. Mike Li
Principal Architect, Altera Corporation

TF-MP3
Design and Verification for Jitter and High-Speed I/Os at Multiple Gbps

Dr. Mike Li, principal architect and distinguished engineer, Altera Corporation, will be at the TecForum to review the latest design and verification developments and technology advancements, with an emphasis on jitter and signal integrity of computer high-speed I/Os (e.g., PCI Express, Serial ATA) and network high-speed I/Os (e.g., GBE, OIF).

Business Forum Panel

Wednesday, February 6
3:45pm - 5:00pm

Laurie Hastings
Senior Manager of Training and Development, Altera Corporation

Title:  "Designing a More Fulfilling Career"

Laurie Hastings, senior manager or training and development at Altera, is participating on a panel at DesignCon that will examine ways companies can and should help employees advance their professional development.  The panel will be moderated by John Epperheimer, a partner at the St. Charles Consulting Group, and will also include representatives from Cadence Design Systems, LSI Logic and TSMC

Visit the DesignCon 2008 website for more information about the event.

Win an iPod touch!

Visit Altera at booth 429 for a chance to win an iPod touch.

Related Links

• Stratix III Device Family
• Stratix III FPGA Low Power Consumption
• Stratix III FPGA DDR3 Support
• Stratix II GX Device Family
• High-Speed Serial I/O Solutions

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