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Date: March 30—April 3, 2009 Featured Technology: Nios® II Embedded Processors, Stratix® IV, Cyclone® III FPGAs Location: McEnery Convention Center, San Jose, CA - Booth 1044 Region: North America Events Event URL: http://esc-sv09.techinsightsevents.com/ |
Visit Altera at the 2009 Embedded Systems Conference (ESC) Silicon Valley, where leading companies showcase cutting-edge hardware, software, tools, and the full spectrum of system components. By attending, you will learn relevant new skills, meet and talk with vendors, network with peers, and develop new strategic partnerships—all under one roof, at one time.
ESC Sponsored Sessions—FREE to registered attendees
Attend Altera's 90-Minute Sponsored Sessions to learn how Altera and Altera's partners can help you to accelerate your embedded designs. Discover how quickly your concepts can become reality using Altera® FPGAs, and see presentations and live demonstrations on several innovative technology topics including:
Designing Embedded Systems with FPGAs—Presented by Rodney Frazer
Tuesday (March 31, 2009) 3:45pm—5:15pm Room C1
Wednesday (April 1, 2009) 2:00pm—3:30pm Room K
This session shows you how to create embedded systems implemented in programmable logic. Learn how to build a processor-based hardware system and run software on it. See how quick and easy it is to build entire systems using Altera’s SOPC Builder tool to configure and integrate hardware intellectual property (IP) blocks.
Designing ARM Embedded Systems in Altera FPGAs/ASICs—Presented by Steven Kravatsky
| Tuesday (March 31, 2009) 5:30pm—7:00pm Room C1 Wednesday (April 1, 2009) 3:45pm—5:15pm Room K |
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This session shows you how to embed Cortex-M1 processors in Altera® Cyclone III FPGAs and ARM7/ARM9 processors in Altera Stratix FPGAs and HardCopy® ASICs. Learn how you can add a Cortex-M1 processor using SOPC Builder and how Arrow's CLS team can provide you with the IP and services to create production-ready ARM solutions in Stratix and HardCopy devices.
Building Embedded Video Systems with FPGAs—Presented by Suhel Dhanani and Xiaofei Dong
Wednesday (April 1, 2009) 8:00am—9:30am Room K
Wednesday (April 1, 2009) 5:30pm—7:00pm Room K
This session shows you the basics of building embedded video systems in programmable logic. Learn about design methodology, system-level tools, and how using video IP blocks can greatly simplify the design process. See how to build a customizable video system that can be dynamically modified using an embedded processor.
Other technical sessions
Fail-Safe FPGA Design Features for High Reliability Systems—Presented by Paul Quintana
Thursday (April 2, 2009) 3:30pm — 4:45pm Room C2
Designing fail-safe data paths within the fabric of a programmable logic device is a significant challenge that adds design constraints and a highly complex certification process. Altera Corporation will share some of the design tool-based capabilities being developed for fail-safe design, and what overhead and design constraints you can expect as a system architect.
Booth demonstrations
Visit the Altera booth to see the latest technology solutions including the industry’s first 40-nm FPGAs and the Altera Embedded Systems Development Kit, Cyclone III Edition (see Figure 1) plus demonstrations on several innovative technology topics including:
- Altera’s embedded soft processor portfolio
- Wind River Linux support for the Nios II processor
- Industry’s first 40-nm FPGA, Stratix IV
- SOPC Builder and Quartus® II the #1 design software in performance and productivity
- Altera Embedded Systems Development Kit, Cyclone III Edition
- MotionFire Motor Control Platform
- Video and image processing with FPGAs
- Consumer and automotive applications
- Altera partners, System Level Solutions and Arrow Electronics
Ask the expert
Have a tough question to ask about designing embedded processor systems using an FPGA? Come ask the expert to get answers to those difficult questions. A team of design specialists will be on hand to answer questions and offer suggestions.
Special Guest James Ball, Chief Architect of the Nios II Processor will be in the Altera booth on Tuesday, March 31, from 2:00 pm to 4:00 pm.
James Ball
Chief Architect of the Nios II Processor
Figure 1. Altera Embedded Systems Development Kit, Cyclone III Edition
