High-Speed Serial Interconnect Seminar
Keynote Speaker
Kevin M. Roselle, CTO, Bayside Design
Kevin Roselle is co-founder and Chief Technical Officer at Bayside Design, Inc., a high-performance interconnect design and analysis consulting company. As CTO, he has employed his experience in EDA tools and high-speed design to lead a team of world-class experts in high-speed package and PCB design, layout, and signal integrity analysis. He has expertise in all aspects of high-speed design including timing analysis, interconnect analysis, crosstalk analysis, electromagnetic modeling of interconnect, packages and connectors, I/O buffer analysis and selection, decoupling analysis, simultaneously switching output analysis, interconnect topology, termination selection, clock distribution and skew analysis, and high-speed bus design. Prior to founding Bayside Design, he was a founding engineer at Chip2Chip which later became Velio Communications, Inc. At Velio, Kevin directed work on several multi-gigabit SERDES and switch fabric chips in packaging, PCB level design, and channel analysis. Before Velio, Kevin was a senior member of consulting staff at Cadence Design Inc, where he worked on the SPECCTRAQUEST™ and SigXplorer™ tools. Kevin also worked at Digital Equipment Corporation in several roles as signal integrity consultant and in software development for SIMPEST, DEC’s internal 2D/3D field solution and modeling tool, as well as for Bell Laboratories in Holmdel, NJ where he was a circuit designer in the teleconferencing and small communications systems departments. Kevin received a BSEE with High Distinction from the University of Nebraska in 1981, and an MSEE from the University of Michigan in 1982.
What to Expect
In this free seminar you will learn the most important principles, design rules, tools, and technology options for designing high-speed serial link interconnects at speeds up to 6.375 Gbps. You will learn from industry experts on how to select and design with connectors, transceivers, and boards for multi-gigabit serial data rates. Key features of Altera’s upcoming transceiver product, Stratix II GX, will also be presented. If you currently design Gbps serial links, or expect to, you will not want to miss this seminar.
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Table 1. Event Agenda
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Time
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Activity
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Speaker
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Title/Company
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8:30 AM
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Breakfast/Registration
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9:00 AM
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Keynote Address
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Kevin M. Roselle
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CTO, Bayside Design
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10:00 AM
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Presentation
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Jim Tavacoli
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Sr. Director, Product Planning, Altera Corp
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10:45 AM
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15-Minute Break
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11:00 AM
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Presentation
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John D'Ambrosia
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Manager, Semiconductor Relations, Tyco
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11:45 AM
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Presentation
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Barry Kirkorian
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Product Manager, Sanmina-SCI Corp
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12:30 PM -
1:30 PM
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Lunch
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Venue Information
Crowne Plaza, Worcester
10 Lincoln Square
Worcester, MA 01608
508-791-1600
www.cpworcester.com
Related Links
If you would like someone to contact you regarding Altera's high-speed solutions, please email workshop@altera.com.
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