Code:DSP Video & Image Processing Seminar
 |
Date: June 21 to 25, 2004
Locations: Toronto, ON, Canada
Boston, MA
San Jose, CA
|
Altera's Code:DSP video and image processing solutions enable designers to develop custom system architectures that increase system performance and lower overall costs. This is a full-day seminar that brings together top global companies and leading-edge products where you can learn about:
- Video and image processing design and integration with system-level design tools, including MATLAB/Simulink
- System integration between FPGAs and digital signal processors
- JPEG2000, MPEG2, MPEG4, H.264 and Windows Media 9 video compression design & integration
- Video interface implementation (including SDI and HD-SDI) using FPGAs
This seminar will include emerging technology demonstrations and presentations by industry experts designed to update and educate engineers, system architects, and project managers on video and image processing solutions.
All attendees will receive a T-shirt and a chance to win a DSP Development Kit, Stratix® II Edition.
| Event Agenda |
| Time |
Activity |
Key Topics Covered |
Presenter |
| 8:30 AM |
Breakfast/Registration |
| 9:00 AM |
Keynote |
|
|
| 9:30 AM |
Video and Image Processing with FPGAs |
- Video and image processing capabilities in FPGAs
- Implementing video interfaces, including HD-SDI, in FPGAs
- System design for video and image processing applications
|
Altera
Brian Jentz |
| 10:15 AM |
Break |
| 10:30 AM |
Nios® II Processor and SOPC Builder |
- Using Altera's Nios II embedded RISC processor and SOPC builder development tool in video and image processing systems
- Demonstration of Nios II processor and SOPC Builder
|
Altera
Alan Calac |
| 11:00 AM |
Image & Video Processing System Design with Simulink & DSP Builder |
- Using model-based design to analyze and optimize algorithm and system-level specifications
- Utilizing simulation test benches to verify real-time behavior of the final system
- Targeting hardware, and demonstration of image processing on Altera development platform
|
The MathWorks and Altera
Dr. Houman Zarrinkoub |
| 11:50 AM |
Lunch |
| 12:45 PM |
Video System Design with FPGAs and DSP -- Video Surveillance Example |
- Key functions in video surveillance -- video capture, MPEG64 compression, motion detection and pre-filtering
- Partitioning systems between FPGAs and digital signal processors
- Optimizing key functions on the FPGA
|
MangoDSP Joel Rotem |
| 1:35 PM |
Design and Integration of High-Definition Decoding on FPGAs |
- Technical aspects of implementing MPEG2 & H.264 Decoders on FPGAs
- Integrating the decoder with the rest of the system
- Demonstration on Altera development platform
|
Amphion
Dr. Jill Cush |
| 2:25 PM |
Break |
| 2:40 PM |
Enabling Real-Time JPEG2000 with FPGA Architectures
|
- JPEG2000 standard and its unique scalability features
- How FPGA and HardCopy® architectures enable acceleration of the JPEG2000 algorithm
- Demonstration of JPEG2000 on Altera development platform
|
Barco
Olivier Cantineau |
| 3:30 PM |
FPGA Co-Processor Development -- H.264 Encoder Example |
- Discussion of key functions in H.264 encoder
- Partitioning the system between FPGAs and digital signal processors
- Co-processor demonstration on Ateme development platform
|
Ateme
Marc Guillaumet |
| 4:20 PM |
Video and Image Co-Processors using 'C' Language and SOPC Builder |
- Designing directly from 'C' to SOPC Builder component to build system-level solutions
- Demonstration of hardware/software design methodology applied to image and video processing applications
- Hardware demonstration using SBS development platform
|
SBS
Larry Maki |
| 5:00 - 7:00 PM |
Demo Room and Refreshments |
Detailed Agenda and Speaker Information
|
Literature
> 
