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Implementing DSP Designs in FPGAs
(IDSP210)
8 Hours
Instructor-Led Course
Course Description
Learn the FPGA design flow for implementing DSP designs. You will use DSP Builder which is an interface between the Quartus® II software v. 7.2 & Mathworks` Matlab & Simulink products. You will analyze, design & implement DSP systems using the DSP Builder blockset in Matlab Simulink. You will incorporate IP cores into your DSP designs by configuring FIR filters, NCO & FFT MegaCore® functions. You will use SignalTap® II logic analyzer & the DSP Development Kit to aid in DSP design. With the Hardware in the Loop feature, you will increase simulation speed by co-simulating a design with a physical FPGA board. With the link for ModelSim feature, you will co-simulate ModelSim RTL-level models from within Matlab & Simulink.
At Course Completion
- Evaluate options for implementing DSP algorithms
- Use DSP Builder to create DSP designs and perform system simulations
- Select, parameterize, and incorporate Altera IP cores into your DSP design
- Co-simulate Matlab/Simulink design with a physical FPGA board by using Altera DSP Builder Hardware in the Loop feature.
- Use FIR, NCO, FFT MegaCore functions
- Complete a DSP system using Altera technology
Skills Required
- Background in digital logic design
- Familiarity with DSP fundamentals and design
- Familiarity with Altera® FPGA architecture is helpful, but not necessary
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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