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The Quartus II Software Design Series: Foundation (Instructor-led Training)
(IDSW110)
8 Hours
Instructor-Led Course
Course Description
You will learn how to use the Quartus® II software v. 8.0 to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, and compile your deisgn. You will also enter basic internal and I/O timing constraints & analyze a design for these timing constraints using TimeQuest, the timing analyzer in the Quartus II software.
You will learn techniques to help you plan your design. You will employ Quartus II features that can help you achieve design goals faster. You will also learn how to plan & manage I/O assignments.
At Course Completion
- Make pre-project decisions to plan design
- Create, manage & compile Quartus II projects
- Plan & manage device I/O assignments using Pin Planner
- Assign clock & I/O constraints to improve design performance
- Analyze clock & input/output timing using TimeQuest
- Review compilation results
Skills Required
- Background in digital logic design
- Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool
- Experience with PCs and the Windows operating system
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
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