Course Description
You will learn how to use the Quartus® II software v. 9.1 to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, and compile your design. You will also learn about timing constraints and analyze a design compiled with these constraints using the TimeQuest timing analyzer, the path-based static timing analysis tool included with the Quartus II software. You will learn techniques to help you plan your design. You will employ Quartus II features that can help you achieve design goals faster. You will also learn how to plan and manage I/O assignments for your target device.At Course Completion
You will be able to:- Make pre-project decisions to plan design
- Create, manage & compile Quartus II projects
- Plan & manage device I/O assignments using Pin Planner
- Assign clock & I/O constraints to improve design performance
- Analyze clock & input/output timing using TimeQuest
- Review compilation results
Skills Required
- Background in digital logic design
- Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool
- Experience with PCs and the Windows operating system
Related Courses
Below are the related courses you may be interested in:- Chinese Version: The Quartus II Software Design Series: Foundation (Online)
- The Quartus II Software Design Series: Foundation (Online Training)
Applicable Training Curriculum
This course is part of the following Altera training curriculum:- ASIC-to-FPGA Designer
- CPLD Designer
- DSP Designer
- Embedded HW Designer
- FPGA Designer
- HardCopy Designer
- Transceivers
Class Schedule
| Result Showing 6 | ||||
|---|---|---|---|---|
| Location | Dates | Price | ||
| San Jose, CA | 4/13/10 | $495 | Register Now | |
| Chelmsford, MA | 4/27/10 | $495 | Register Now | |
| Arrow- Tempe, AZ | 5/11/10 | $495 | Register Now | |
| Richardson, TX | 5/11/10 | $495 | Register Now | |
| Schaumburg, IL | 6/16/10 | $495 | Register Now | |
| Denver, CO | 8/10/10 | $495 | Register Now | |
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