Course Description
You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus® II software v. 9.1. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.At Course Completion
You will be able to:- Understand the TimeQuest timing analyzer timing analysis design flow
- Apply basic and complex timing constraints to an FPGA design
- Analyze an FPGA design for timing using the TimeQuest timing analyzer
- Write and manipulate SDC files for analysis and controlling the Quartus II compilation
Prerequisites
We recommend completing the following courses:- The Quartus II Software Design Series: Foundation (Instructor-led Training)
- The Quartus II Software Design Series: Foundation (Online Training)
Skills Required
- Experience with PCs and the Windows operating system
- Completion of "The Quartus II Software Design Series: Foundation" online or instructor-led course OR a working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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|---|---|---|---|---|
| Location | Dates | Price | ||
| San Diego, CA | 4/22/10 | $495 | Register Now | |
| Arrow- Tempe, AZ | 5/12/10 | $495 | Register Now | |
| Chelmsford, MA | 5/25/10 | $495 | Register Now | |
| San Jose, CA | 6/8/10 | $495 | Register Now | |
| Schaumburg, IL | 6/17/10 | $495 | Register Now | |
| Denver, CO | 8/11/10 | $495 | Register Now | |
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