|
|
 |
The Quartus II Software Design Series: Verification
(IDSW130)
8 Hours
Instructor-Led Course
Course Description
You will learn features of the Quartus® II software v. 8.0 & ModelSim® software that will enable you to verify your FPGA design*. You will learn how to simulate your design using the ModelSim-Altera simulator as well as understand what is required to simulate in other EDA simulation tools. You will learn how to use projects in the ModelSim-Altera tool & simulate Altera® libraries. You will also estimate FPGA power consumption using tools found in the Quartus II software. You will use debugging tools available in the Quartus II software, such as the SignalTap® II embedded logic analyzer & the Logic Analyzer Interface, & select the correct tool to effectively debug your design. *Some (not all) features examined by this course apply to CPLD designs
At Course Completion
- Simulate a design using the ModelSim-Altera simulator
- Analyze power consumption with the PowerPlay power analyzer
- Debug designs in-system using the SignalTap II embedded logic analyzer
- Connect internal debug nodes to an external logic analyzer using the Logic Analyzer Interface
- View & edit embedded memory contents using the In-System Memory Content Editor
- Make incremental design changes with Chip Planner
Prerequisites
We recommend completing the following courses:
Skills Required
- Experience with PCs and the Windows operating system
- Completion of "The Quartus II Software Design Series: Foundation" course OR a working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
|
|
|
Literature
> 
