Course Description
This one-day class is a general introduction to the VHDL language and its use in logic design, covering constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of VHDL so that you can begin creating your own designs, using both behavioral and structural approaches. In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing simple but practical designs. You will check your designs by compiling in the Quartus® II software v. 9.1 and simulating in the ModelSim®-Altera® tool.At Course Completion
You will be able to:- Understand simulation versus synthesis environments
- Build basic VHDL models using the VHDL design units (entity, architecture, configuration, package)
- Use behavioral modeling constructs and techniques to describe logic functionality
- Use structural modeling constructs and techniques to create hierarchical designs
Skills Required
- Background in digital logic design
- Knowledge of simulation is a plus
- Prior knowledge of a programming language (e.g., "C" language) is helpful, but not required
- No prior knowledge of VHDL or Quartus II software is needed
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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| Location | Dates | Price | ||
| Schaumburg, IL | 6/15/10 | $495 | Register Now | |
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