Course Description
This one-day class is a general introduction to the VHDL language and its use in programmable logic design, covering constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of VHDL so that you can begin creating your own designs, using both behavioral and structural approaches. In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing simple but practical designs. You will check your designs by compiling in the Quartus® II software v. 11.1 and simulating in the ModelSim®-Altera® tool.At Course Completion
You will be able to:- Write synthesizable RTL code
- Create state machines and control their encoding
- Optimize designs to improve resource usage and performance
- Develop simple testbenches to perform RTL debugging
- Create parameterizable VHDL modules
- Synthesize and place & route designs using the Altera flow
- Analyze designs in ModelSim-Altera software
Skills Required
- Background in digital logic design
- Knowledge of simulation is a plus
- Prior knowledge of a programming language (e.g., "C" language) is helpful, but not required
- No prior knowledge of VHDL or Quartus II software is needed
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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| Location | Dates | Price | ||
| San Jose, CA (Instructor-Led) | 4/11/12 | $495 | Register Now | |
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