|
|
 |
Introduction to Verilog HDL
(IHDL120)
8 Hours
Instructor-Led Course
Course Description
You will learn how to implement basic constructs and modeling structures in Verilog to create an optimal FPGA design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about the simulation constructs. You will also learn how to take advantage of various features in Verilog HDL such as delays in programmable logic design. You will gain hands-on experience by implementing various simple but practical designs. You will gain a basic understanding of Verilog HDL to enable you to begin writing designs. In addition you will create a new project, enter in a new design, compile and simulate your design using the Quartus® II software v. 6.0 development tool.
At Course Completion
- Implementing simple Verilog HDL designs
- Creating an optimal design for synthesis using Verilog HDL
- Creating and compiling projects using the Quartus II software
- Analyzing a design using the Quartus II simulator
Skills Required
- Background in digital logic design
- Knowledge of simulation is a plus
- Prior knowledge of a programming language (e.g., "C" language) is a plus
- No prior knowledge of Verilog HDL is needed
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
|
|
|
Literature
> 
