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Advanced Verilog Design Techniques
(IHDL230)
8 Hours
Instructor-Led Course
Course Description
In this course you will learn efficient coding techniques for writing synthesizable Verilog, particularly for Altera® devices. You will gain experience in writing behavioral and structural code and implementing state machines with multiple efficient coding styles. You will learn about test benches and the techniques to build them. You will also learn how to optimize a design to an FPGA. With hand-on exercises, you will write synthesizable RTL code, explore different coding schemes for design efficiency, write test benches and test cases and run functional simulation. You will synthesize, place and route the design and finally perform gate-level timing simulation. You will use the Quartus® II software v. 7.2 for the exercises.
At Course Completion
- Implementing designs with FPGA megafunctions
- Implementing synthesizable sequential and combinatorial RTL code
- Implementing finite state machines using multiple encoding scheme
- Developing test benches and test cases
- Running functional simulations and debugging RTL code
- Running synthesis and place & route using the Quartus II software
- Running gate-level simulation with SDF back-annotation
Prerequisites
We recommend completing the following courses:
Skills Required
- Completion of the "Introduction to Verilog HDL" course or some prior knowledge and use of Verilog hardware description language (HDL)
- Background in digital logic design
- Understanding of synthesis and simulation processes
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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