Course Description
In this course, you will learn efficient coding techniques for writing synthesizable Verilog. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions including registered, memory and arithmetic functions. You will learn how to use Verilog constructs to parameterize your design, increasing their flexibility and reusability. While the concepts presented will mainly be targeting Altera® devices using the Quartus® II software, many can be applied to other synthesis tools as well. You will be introduced to testbenches and Verilog constructs used when building them. The hands-on exercises will use the Quartus II software version 9.0 to synthesize Verilog code and the ModelSim®-Altera tool for simulation.At Course Completion
You will be able to:- Implementing synthesizable sequential and combinatorial RTL code
- Implementing finite state machines using multiple encoding schemes
- Debugging RTL code for common errors
- Developing simple testbenches for verification
- Using the Quartus II software to synthesis and verify results
- Running functional simulations in the ModelSim-Altera software
Prerequisites
We recommend completing the following courses:Skills Required
- Completion of the "Introduction to Verilog HDL" course or some prior knowledge and use of Verilog hardware description language (HDL)
- Background in digital logic design
- Understanding of synthesis and simulation processes
Applicable Training Curriculum
This course is part of the following Altera training curriculum:No class is being offered at this time
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