Course Description
You will learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools. You will gain experience writing behavioral & structural code & learn to effectively code common logic functions including registers, memory, & arithmetic functions. You will use VHDL constructs to parameterize your designs to increase their flexibility & reusability. You will also be introduced to testbenches, VHDL constructs used to build them, & common ways to write them. The exercises will use the Quartus II software version 11.1 to process VHDL code & ModelSim®-Altera software for simulation.At Course Completion
You will be able to:- Develop coding styles for efficient synthesis when:
- Targeting device features
- Inferring logic functions
- Using arithmetic operators
- Writing state machines
- Use Quartus II software RTL Viewer to verify correct synthesis results
- Incorporate Altera structural blocks in VHDL designs
- Write simple testbenches for verification
- Create parameterized designs
Prerequisites
We recommend completing the following courses:Skills Required
- Completion of the "Introduction to VHDL" course or some prior knowledge and use of VHDL
- Background in digital logic design
- Understanding of synthesis and simulation processes
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
| Result Showing 3 | ||||
|---|---|---|---|---|
| Location | Dates | Price | ||
| Virtual Classroom | 6/26/12 - 6/27/12 | $495 | Register Now | |
| Virtual Classroom | 9/19/12 - 9/20/12 | $495 | Register Now | |
| Virtual Classroom | 11/13/12 - 11/14/12 | $495 | Register Now | |
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