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Advanced VHDL Design Techniques
(IHDL240)
8 Hours
Instructor-Led Course
Course Description
You will learn efficient coding techniques for VHDL synthesis, particularly for Altera® devices. You will gain experience writing behavioral and structural code and learn how to effectively code common logic functions including registered, memory, and arithmetic functions. You will also be introduced to testbenches and common ways to write them. This course was designed independent of synthesis and simulation tools, although the hands-on exercises will mainly use Quartus® II software v. 6.1 for processing of VHDL code and Mentor Graphic’s ModelSim® software for simulation.
At Course Completion
- Develop coding styles for efficient synthesis when:
- Targeting device features
- Inferring logic functions
- Using arithmetic operators
- Writing state machines
- Use Quartus II software RTL Viewer to verify correct synthesis results
- Implement intellectual property (IP) and other functions in VHDL designs
- Write testbenches for verification
- Write parameterized designs
Prerequisites
We recommend completing the following courses:
Skills Required
- Completion of the "Introduction to VHDL" course or some prior knowledge and use of VHDL
- Background in digital logic design
- Understanding of synthesis and simulation processes
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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