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Interfacing to External Memory with Altera FPGAs (IMEM210)
8 Hours Instructor-Led Course

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Course Description

You will learn to implement external memory interfaces with Altera® FPGAs & the Quartus® II software version 9.1. The course provides lecture & lab exercises to help you understand the design flows, your options, & the challenges you may face. Since Double Data Rate (DDR) interfaces are most prevalent, they are the focus of the class. Nonetheless, RLDRAM II, SRAM, and QDRII/+ will also be touched upon. Through a series of lab exercises, you will learn to implement a “High Performance” DDR SDRAM controller with auto-calibrating phy block. You will also learn how to take advantage of the self-service resources available, which should improve your confidence that you can successfully complete a memory interfacing design on your own.

At Course Completion

You will be able to:
  • Understand the external memory interface options & how to choose one (eg. DDR 1, 2, 3, RLDRAM II, QDR II/+, SRAM)
  • Implement the high performance DDR SDRAM controller using the MegaWizard® plug-in manager
  • Verify controller functionality with the ModelSim simulator
  • Close timing on your design
  • Connect your own logic to the High Performance controller
  • Implement multiple controllers in a single FPGA
  • Learn how to use the controller within SOPC Builder

Prerequisites

We recommend completing the following courses:
  • Overview of Mentor Graphic's ModelSim Software
  • The Quartus II Software Design Series: Foundation (Instructor-led Training)
  • The Quartus II Software Design Series: Foundation (Online Training)
  • The Quartus II Software Design Series: Timing Analysis
  • The Quartus II Software Design Series: Verification

Skills Required

  • Background in digital logic design and memory device types
  • Working knowledge of the Quartus II software, especially the TimeQuest static timing analyzer
  • Some knowledge of how to use a hardware simulator (eg. Mentor Graphics ModelSim® software)

Applicable Training Curriculum

This course is part of the following Altera training curriculum:
  • ASIC-to-FPGA Designer
  • FPGA Designer
  • Transceivers

Class Schedule

Result Showing 2                                                                                                                                  
Location Dates Price  
Arrow, Baie DUrfe, QC Canada4/20/10$495Register Now
San Jose, CA6/9/10$495Register Now

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