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Interfacing to External Memory with Altera FPGAs
(IMEM210)
8 Hours
Instructor-Led Course
Course Description
You will learn to implement external memory interfaces with Altera® FPGAs & Quartus® II software 7.1. The course provides lecture & lab exercises to help you understand the design flows, your options, & the challenges you will face. Since Double Data Rate (DDR) interfaces are most prevalent, we will focus on implementing DDR 1 & 2 memory interfaces.
You will learn the memory interface options you have & how to implement a “High Performance” DDR or DDR2 SDRAM controller with auto-calibrating phy block. This type of memory controller exploits the ALTMEMPHY core to achieve the highest system bandwidth.
You will also learn how to take advantage of the self-service resources available. This should improve your confidence that you can successfully complete a memory interfacing design.
At Course Completion
- Understand the external memory interface options & how to choose one (eg. DDR 1, 2, 3, RLDRAM II, QDR II, or SRAM)
- Implement the high performance DDR SDRAM controller using the MegaWizard® plug-in manager
- Verify controller functionality with the ModelSim simulator
- Close timing on your design
- Connect your own logic to the High Performance controller
- Implement multiple controllers in 1 FPGA
- Learn how to use the controller within SOPC Builder
Prerequisites
We recommend completing the following courses:
Skills Required
- Background in digital logic design and memory device types
- Working knowledge of the Quartus II software, especially the TimeQuest static timing analyzer
- Some knowledge of how to use a hardware simulator (eg. Mentor Graphics ModelSim® software)
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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