Course Description
Learn the best ways to maximize productivity throughout the FPGA design cycle, while also maximizing design performance. Using a recommended design methodology as a framework, see what is involved at a high level in preparing to create an FPGA design and what is required to implement it - from the creation of the design specification all the way to final sign-off. Examples and demonstrations will be used throughout the course to provide a reference point for implementing high performance FPGA designs. These include the use of Altera devices and tools, namely the Quartus® II software v11.0, for maximizing your productivity.At Course Completion
You will be able to:- Implement recommended methodologies throughout the FPGA project management process to maximize productivity
- Follow recommended HDL coding practices
- Start creating reusable IP
- Start performing functional verification for designs & IP using testbenches & functional coverage
- Organize a design into logical partitions to exploit incremental compilation
- Implement a plan to close timing
- Implement I/O & board design in tandem with FPGA
- Select appropriate in-system debugging tools
Skills Required
- Background in digital logic design
- Basic knowledge about ASIC or programmable logic design, in particular HDL coding using VHDL or Verilog HDL
- Some experience in managing project resources and personnel
No class is being offered at this time
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