Course Description
Design security and reliability are becoming increasingly important. Designs must be able to prevent tampering and take action if an intruder tries to tamper with or reverse engineer the design. Reliability, usually through design redundancy and often requiring multiple chips, can prevent downtime. In this course, you will learn about the Cyclone III LS device family and how to use the Quartus® II software v. 11.1 to develop secure, reliable designs on a single chip using the Design Separation Flow. This design flow leverages Quartus II incremental compilation and the unique security features of Cyclone III LS devices. You'll learn how to plan for Design Separation, organize your design floorplan, and make correct security assignments. This class can be taught onsite for $2500.At Course Completion
You will be able to:- Understand the unique security features of the Cyclone III LS device family to support the design separation flow
- Make pre-project decisions for design separation
- Create a floorplan and I/O assignments for separation
- Create security assignments for a design
- Review compilation results to ensure security requirements were met
Prerequisites
We recommend completing the following courses:- Introduction to Incremental Compilation
- The Quartus II Software Design Series: Optimization
- Using the Quartus II Software: An Introduction
- Using the Quartus II Software: Chip Planner
Skills Required
- Background in Quartus II software
- Quartus II incremental compilation knowledge
- LogicLock knowledge
- Experience using Chip Planner & Design Partition Planner preferred
Applicable Training Curriculum
This course is part of the following Altera training curriculum:No class is being offered at this time
Request a class in your region
