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High-Speed Design Using Stratix II GX Devices
(ISIIGX210)
8 Hours
Instructor-Led Course
Course Description
An increasing number of FPGA-based designs are incorporating high-speed serial protocols running at speeds above 6 Gbps. These protocols have well-defined hardware specifications which you must meet. However, you may want to implement your own protocol solution as a variation of an existing protocol or as a completely customized solution. Stratix® II GX devices allow you to do this. In this advanced course, you will implement your own custom high-speed serial I/O protocol using Stratix II GX multi-gigabit transceivers in basic mode configuration. You will learn transceiver architectural details, transceiver feature settings & design techniques to optimize your high-speed serial link. You will compile & analyze designs using Quartus® II software v 7.2 & a 6.375 Gbps device.
At Course Completion
- Implement your own custom high-speed serial protocol at speeds up to 6.375 Gbps
- Configure transceiver analog physical media access (PMA) features such as serialization/deserialization, clock data recovery (CDR), phase locked loops (PLLs), pre-emphasis, and equalization
- Configure transceiver digital physical coding sub-layer (PCS) functions such as word alignment, channel alignment, rate matching, and 8B/10B encoding/decoding
Prerequisites
We recommend completing the following courses:
Skills Required
- Basic familiarity with high-speed serial I/O protocols and standards, such as PCI Express or Gigabit Ethernet
- Working knowledge of design entry and compilation using the Quartus II software
- Background in high-speed design, digital logic, and board design
- Experience with PCs and the Windows operating system
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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