Course Description
This course has Simplified Chinese audio. This 8 hour online training will show you how to use the Quartus® II software v. 9.1 to develop an FPGA or CPLD. The course is segmented and easy to navigate. You will create a new project and enter in a new or existing design. You will also enter basic internal and I/O timing constraints & analyze a design for these timing constraints using the TimeQuest timing analyzer. You will learn techniques to help you plan your design. You will employ Quartus II features that can help you achieve design goals faster. You will also learn how to plan & manage I/O assignments.At Course Completion
You will be able to:- Make pre-project decisions to plan design
- Create, manage & compile Quartus II projects
- Review compilation results
- Plan & manage device I/O assignments using Pin Planner
- Assign clock & I/O constraints to improve design performance
- Analyze clock & input/output timing using the TimeQuest timing analyzer
Skills Required
- Background in digital logic design
- Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool
- Experience with PCs and the Windows operating system
Applicable Training Curriculum
This course is part of the following Altera training curriculum:- ASIC-to-FPGA Designer
- CPLD Designer
- Embedded HW Designer
- FPGA Designer
- HardCopy Designer
- Transceivers
Class Schedule
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| Location | Dates | Price | ||
| On-line | Any Time | Free | Register Now | |
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