Course Description
This course has Simplified Chinese audio. You will use the TimeQuest static timing analyzer tool in the Quartus® II software v. 6.1 to verify performance of an FPGA or structured ASIC. You will also create timing constraints (i.e. assignments) using TimeQuest. You will use supported Synopsys Design Constraints (SDCs) and generate timing reports from the TimeQuest user interface and from script files.At Course Completion
You will be able to:- Use TimeQuest to perform timing analysis when targeting an Altera FPGA or structured ASIC
- Constrain a design using the TimeQuest-supported SDC commands to control fitting and for comparison of timing results
- Create timing constraints using the TimeQuest GUI
- Generate timing reports in TimeQuest and interpret them to verify internal and I/O device performance
Prerequisites
We recommend completing the following courses:Skills Required
- Background in digital logic design
- Experience with PCs & the Windows operating system
- An understanding of basic FPGA design flow
- One of the following:
- Completion of the "Chinese Version: Using the Quartus II Software: An Introduction" online training course
- Completion of the tutorial available in the Quartus II software online help
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:- ASIC-to-FPGA Designer
- CPLD Designer
- Embedded HW Designer
- FPGA Designer
- HardCopy Designer
- Transceivers
Class Schedule
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| Location | Dates | Price | ||
| On-line | Any Time | Free | Register Now | |
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