时序逼近最佳HDL设计实践 (Chinese Version of Best HDL Design Practices for Timing Closure) (OCHDL1130)
1 Hour Online Course

Course Description

学习怎样采用HDL设计方法来解决时序逼近问题。这一培训课程将讨论时序逼近问题，解释为什么规划好时序逼近非常重要。您将学习常见的时序逼近问题。您将了解怎样通过修改函数代码，改变实际时序逼近环境。学习Quartus® II 软件v9.1 怎样帮助您实现这一目标。

At Course Completion

You will be able to:

• 找到导致时序逼近问题的HDL结构
• 适当的修改HDL代码来解决这类问题

Prerequisites

We recommend completing the following courses:

• Chinese Version: VHDL Basics
• Verilog HDL基础 (Chinese Version of Verilog HDL Basics)
• 使用Quartus II软件：入门 (Chinese Version of Using the Quartus II Software: An Introduction)

Skills Required

• 数字逻辑设计背景知识
• 基本掌握FPGA设计流程
• 基本掌握Quartus II 用户界面
• 基本掌握Verilog HDL或者VHDL编程

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

• ASIC-to-FPGA Designer
• FPGA Designer

Class Schedule

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Location	Dates	Price
On-line	Any Time	Free	Register Now

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