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I/O Management
(ODSW1107)
1 Hour
Online Course
Course Description
By the end of this training, you will be familiar with most of the I/O management features found in Quartus® II software version 6.1. A complete early I/O planning design flow is introduced that builds on the Pin Planner megafunction & IP MegaCore® function creation capability introduced in version 6.0 of the Quartus II software. Advanced I/O Timing is a new option that works with the TimeQuest Timing Analyzer to produce enhanced timing reports based on I/O assignments & characteristics along with a board trace model that defines PCB components & settings. The enhanced reports include board signal integrity metrics that can assist in making I/O assignments & board design decisions. Finally, you’ll be directed to more sources for information about I/O management & signal integrity.
At Course Completion
- Create a top-level netlist file from a project that includes only reserved pins or megafunctions or IP MegaCores created in the Pin Planner.
- Use this top-level netlist file as the basis for a project revision or an entire new project.
- Enable the Advanced I/O Timing option and configure board trace models.
- Use calculated signal integrity metrics from the Advanced I/O Timing option as a guide for designing the PCB to support the FPGA design with good signal integrity.
Prerequisites
We recommend completing the following courses:
Skills Required
- Completion of “Using the Quartus II Software: An Introduction” OR a basic understanding of the FPGA design flow and the Quartus II software
- Use of the Assignment Editor and, preferably, the Pin Planner (Megafunction and IP MegaCore function creation)
-Volume 2, I/O Management chapter of the Quartus II Handbook
- Knowledge of board-level signal integrity issues and design techniques
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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