I/O System Design

Course Description

You will learn the I/O management features found in Quartus® II software v. 8.1. An I/O planning flow is used for the I/O planning tasks required for a typical FPGA design. A complete early I/O planning design flow is introduced that details how to create & import megafunctions & IP MegaCore® functions into the Pin Planner to generate a complete I/O port description for a design. The I/O creation, modification, & validation features available in the Pin Planner will also be discussed. Advanced I/O Timing, a feature that works with the TimeQuest Timing Analyzer to produce enhanced timing reports, is presented. The enhanced reports generated by this feature include board signal integrity metrics that can assist in making I/O assignments & board design decisions.

At Course Completion

You will be able to:

Create a top-level design file from a project that includes validated reserved I/O pins & instantiated megafunctions or MegaCore functions without writing any HDL code
Use this top-level design file as the basis for a project revision or a new project
Create, manage, & verify I/O-related assignments
Enable the Advanced I/O Timing option & configure board trace models
Use signal integrity metrics from the Advanced I/O Timing option to design the PCB with good signal integrity

Prerequisites

We recommend completing the following courses:

Skills Required

Completion of “Using the Quartus II Software: An Introduction” OR a basic understanding of the FPGA design flow and the Quartus II software
Basic understanding of timing analysis using the TimeQuest timing analyzer
Knowledge of board-level signal integrity issues and design techniques

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

Class Schedule

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Location	Dates	Price
On-line	Any Time	Free	Register Now

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I/O System Design (ODSW1107) 2 Hours Online Course