Course Description
This training builds on the topics discussed in "I/O System Design." You will learn about the need for signal integrity simulation & analysis when designing high-speed PCBs. You will learn what simultaneous switching noise (SSN) is and the tools available to reduce or eliminate it. The three types of signal integrity analysis possible with the Quartus® II software v. 9.0 are reviewed. You will learn how to create simulation models, what the double counting problem is that is inherent in model creation & how to solve it. IBIS & HSPICE models are compared. You will learn the design flow for signal integrity with third-party tools including creation & customization of simulation models. Finally, you'll learn recommendations to run & analyze simulations in third-party tools.At Course Completion
You will be able to:- Analyze an FPGA design for SSN & know how to reduce or eliminate SSN
- Configure the Quartus II software to generate IBIS or HSPICE model files
- Generate the selected model file type
- Customize the output file(s) for use in simulations
- Create & run simulations in Mentor Graphics HyperLynx and Synopsys HSPICE, integrating the simulation models generated
- Improve the results of signal integrity simulations
- Use simulation results as a guide for designing the PCB
Prerequisites
We recommend completing the following courses:Skills Required
- Completion of “Using the Quartus II Software: An Introduction” OR a basic understanding of the FPGA design flow & the Quartus II software
- Basic knowledge of board-level signal integrity issues & design techniques (i.e. signal termination techniques, routing constraints, etc.)
- Familiarity with your third-party board simulation tool of choice (Mentor Graphics HyperLynx, Synopsys HSPICE)
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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