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Home > Education & Events > Course Print This Page Subscribe to Email Early Pin Planning with Pin Planner in the Quartus II Software (ODSW1112) 0.5 Hours Online Course Course Description This training will teach you how to be successful with early pin planning for your design cycle using the Quartus® II software v. 7.2. You will learn how to overcome I/O planning challenges. The early pin planning flow will be discussed. This includes: design entry for top level ports, definition of connections, creation of top level HDL files, pin assignments, and validation of pin assignments. At Course Completion Understand the benefits of early pin planning with the Pin Planner tool Import and edit Altera® Intellectual Property (IP) pin-assignments into Pin Planner Create a top level file in Pin Planner Create and validate pin assignments Prerequisites We recommend completing the following courses: I/O Management The Quartus II Software Design Series: Foundation (Online Training) Using the Quartus II Software: An Introduction Skills Required Familiarity with the Quartus II Software Some understanding of Hardware Description Languages (Verilog or VHDL) Some understanding of the I/O planning process Applicable Training Curriculum This course is part of the following Altera training curriculum: Asic-to-FPGA Designer Embedded HW Designer FPGA Designer HardCopy Designer High-Speed IO Designer Class Schedule Result Showing 1 Location Dates Price   On-line Any Time Free Register Now Request a class in your region Rate This Page

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