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TimeQuest Timing Analyzer
(ODSW1115)
1.5 Hours
Online Course
Course Description
You will learn how to use the TimeQuest static timing analyzer tool in the Quartus® II software v. 7.2 to verify performance of an FPGA or structured ASIC. You will learn how to create timing constraints in Synopsys Design Constraint (SDC) format easily using the TimeQuest graphical user interface tools. You will generate timing reports with the tools available in the TimeQuest user interface and from script files.
At Course Completion
- Use the TimeQuest timing analyzer to perform timing analysis when targeting an Altera FPGA or structured ASIC
- Constrain a design using SDC commands to control fitting and for comparison of timing results
- Create timing constraints using the TimeQuest GUI
- Generate timing reports and interpret them to verify internal and I/O device performance
Prerequisites
We recommend completing the following courses:
Skills Required
- Background in digital logic design
- Experience with PCs & the Windows operating system
- An understanding of basic FPGA design flow
- One of the following:
- Completion of the "Using the Quartus II Software: An Introduction" online training course
- Completion of "The Quartus II Software Interactive Tutorial"
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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