Course Description
You will learn how to use the TimeQuest static timing analyzer tool in the Quartus® II software v. 9.1 to verify performance of an FPGA or HardCopy® ASIC. You will learn how to create timing constraints in Synopsys Design Constraint (SDC) format easily using the TimeQuest graphical user interface tools. You will generate timing reports with the tools available in the TimeQuest user interface and from script files.At Course Completion
You will be able to:- Use the TimeQuest timing analyzer to perform timing analysis when targeting an Altera FPGA or HarcCopy ASIC
- Constrain a design using SDC commands to control fitting and for comparison of timing results
- Create timing constraints using the TimeQuest GUI
- Generate timing reports and interpret them to verify internal and I/O device performance
Prerequisites
We recommend completing the following courses:- The Quartus II Software Design Series: Foundation (Online Training)
- The Quartus II Software Interactive Tutorial
- Using the Quartus II Software: An Introduction
Skills Required
- Background in digital logic design
- Experience with PCs & the Windows operating system
- An understanding of basic FPGA design flow
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:- ASIC-to-FPGA Designer
- CPLD Designer
- Embedded HW Designer
- FPGA Designer
- HardCopy Designer
- Transceivers
Class Schedule
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| On-line | Any Time | Free | Register Now | |
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