Course Description
You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature of the Quartus® II software version 9.1. By the end of this training, you will be able to use LogicLock™ regions in physical partitioning of your design. You will be able to decide when and when not to use incremental compilation, how to set up your design hierarchy and source code to support incremental compilation, and how to segment your design into logical design partitions. You will also be able to apply the incremental compilation methodology to both the top-down and bottom-up design flows.At Course Completion
You will be able to:- Create & manage LogicLock regions to physically partition a design
- Create & manage good design partitions
- Determine whether your next design can benefit from incremental compilation
- Set up & perform incremental compilation
- Use incremental compilation in the top-down & bottom-up design flows
- Set up a top-level project with constraints for a team-based design flow
- Generate bottom-up design partition scripts
- Export a lower-level design & import it into the top-level design
Prerequisites
We recommend completing the following courses:Skills Required
- Background in digital logic design
- Familiarity with using the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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