Course Description
This training will introduce you to the Quartus® II v.8.1 software Chip Planner. You will learn about the Chip Planner tasks, layers, and views. You will learn how to perform design analysis with Chip Planner. Specifically you will see how to view critical paths and physical timing estimates. You will see how to use Chip Planner to perform power analysis and to view routing congestion. Next, you will learn to work with floorplan assignments, including LogicLock™ regions. Finally, you will learn how to perform ECOs (Engineering Change Orders).At Course Completion
You will be able to:- Perform design analysis with Chip Planner
- Perform ECOs in Chip Planner
- Work with location assignments & LogicLock regions
Prerequisites
We recommend completing the following courses:Skills Required
- One of the following:
- Completion of the "Using the Quartus II Software: An Introduction" online training course
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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| Location | Dates | Price | ||
| On-line | Any Time | Free | Register Now | |
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