Using the Quartus II Software: Chip Planner (ODSW1155)
1 Hour Online Course

Course Description

This training will introduce you to the Quartus® II software version 11.0 Chip Planner. You will learn how to analyze your design using the Chip Planner features such as floorplan views, critical path analysis and routing congestion analysis. Next you will learn how to create and control LogicLock™ regions using the Chip Planner. Finally, you will learn to use the Chip Planner along with other Quartus II integrated tools to perform Engineering Change Orders.

At Course Completion

You will be able to:

• Perform design analysis with Chip Planner
• Work with location assignments & LogicLock regions
• Perform Engineering Change Orders (ECOs) in Chip Planner along with Quartus II integrated tools such as the Resource Property Editor and Change Manager

Prerequisites

We recommend completing the following courses:

• Using the Quartus II Software: An Introduction

Skills Required

• Completion of “Using the Quartus II Software: An Introduction” OR
• Understanding or knowledge of:
• Quartus II software and Altera devices
• Quartus II Engineering Change Order (ECO) flow
• Location assignments & LogicLock methodology with Timing Closure Floorplan

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

• ASIC-to-FPGA Designer
• FPGA Designer

Class Schedule

Result Showing 1
Location	Dates	Price
On-line	Any Time	Free	Register Now

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