Constraining and Analyzing Timing for Source Synchronous Circuits with TimeQuest (ODSW1160)
1 Hour Online Course

Course Description

This training will show you how to constrain and analyze source synchronous interfaces with the TimeQuest timing analyzer in the Quartus® II software v. 6.1. You will learn the benefits of source synchronous interfaces as compared to common clock system interfaces. You will be able to write SDC constraints to constrain single data rate source synchronous outputs and inputs. You will also learn to use the TimeQuest timing analyzer to report and analyze timing for source synchronous outputs and inputs.

At Course Completion

You will be able to:

• Describe basic functionality of a source synchronous interface
• Constrain single data rate source synchronous interfaces with SDC constraints
• Analyze timing for single data rate source synchronous interfaces with the TimeQuest timing analyzer

Prerequisites

We recommend completing the following courses:

• TimeQuest Timing Analyzer

Skills Required

• Completion of “TimeQuest Timing Analyzer” online training OR
• Understanding or knowledge of:
• Static timing analysis concepts
• How to create SDC constraints for clocks and IOs
• Using the TimeQuest timing analyzer

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

• FPGA Designer
• HardCopy Designer
• ASIC-to-FPGA Designer

Class Schedule

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Location	Dates	Price
On-line	Any Time	Free	Register Now

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