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SignalTap II Embedded Logic Analyzer
(ODSW1164)
1.5 Hours
Online Course
Course Description
This training will present the benefits the SignalTap® II logic analyzer provides for on-chip debugging using the Quartus® II software v. 7.2. Upon completion of this training, you will be able to recognize and know how to perform the major tasks required for a SignalTap II debugging process flow. You will also know where to go to find additional support and information resources.
At Course Completion
- Add one or more instances of the SignalTap II logic analyzer to a design
- Configure the SignalTap II logic analyzer to debug the design
- Use the logic analyzer with incremental compilation to reduce recompile times
- Operate the SignalTap II logic analyzer to capture data as defined by the trigger settings
- Analyze data captured by the trigger condition(s) & use it to locate & fix bugs in the design
- Use the state-based triggering flow and Power-Up triggers
Prerequisites
We recommend completing the following courses:
Skills Required
- Basic knowledge of the Quartus II software including incremental compilation, the Nios® II processor and the Nios II IDE (optional)
- Knowledge of external logic analyzer operations (optional)
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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